Correction of block errors for a system having non-volatile memory

• US 9,069,695 B2
• Filed: 03/14/2013
• Issued: 06/30/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Vogan, Andrew W., Post, Daniel J.
• Primary Examiner(s): MCMAHON, DANIEL F
• Application Number:
  US13/829,088
• Publication Number:
  US 20140281814A1
• Time in Patent Office: 838 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Systems and methods are disclosed for correction block errors. In particular, a system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This can be a space efficient approach for recovering from single-block data errors such as, for example, single-page uncorrectable error-correcting codes (“uECCs”) and/or errors caused by word line shorts.

Claims

1. A method for correcting data errors in a non-volatile memory (“

NVM”

) comprising a plurality of blocks, the method comprising;

detecting an error in a first page of a block of the plurality of blocks of the NVM, the block having a pre-determined number of page-modulo XOR (“

PMX”

) parity pages;

identifying a first set of pages of the block having modulo value that is the same as the first page;

reading first data from the first set of pages of the block;

reading second data from a corresponding PMX parity page of the block; and

performing an XOR function based on the first data and the second data to recover third data stored in the first page,

wherein the error is associated with one of a word line short in the NVM and a single-page uncorrectable error-correcting code (“

uECC”

).

2. The method of claim 1, further comprising detecting the error in a second page, wherein the second page shares a word line with the first page.

3. The method of claim 1, further comprising detecting the error in a second page, wherein the second page has a word line adjacent to a word line of the first page.

4. The method of claim 1, wherein the PMX parity page encompasses the first page and the first set of pages.

5. The method of claim 1, wherein the PMX parity page is a particular page of the block.

6. The method of claim 5, wherein the identifying the first set of pages of the block is performed according to:

a mod n=m,

wherein n is the pre-determined number of PMX parity pages in the block, m is the modulo value, and a is a page number of a page from the first set of pages.

7. The method of claim 6, wherein the PMX parity pages are located at the end of the block.

8. The method of claim 6, wherein n is one of eight and twelve.

9. A system comprising:

non-volatile memory (“

NVM”

) comprising a band, wherein the band comprises a plurality of stripes; and

memory interface comprising control circuitry operative to;

detect whether read errors are localized to a block of the band wherein the errors are associated with one of a word line short in the NVM and a single-page uncorrectable error-correcting code (“

uECC”

);

in response to detecting that the read errors are localized to the block of the NVM, read first data associated with a set of stripes of the band, wherein the first data excludes a page with one of the read errors;

read second data from a parity page of the band corresponding to the set of stripes; and

perform a reversible function using the first data and the second data in order to recover third data on the page.

10. The system of claim 9, wherein the page is located in the block.

11. The system of claim 9, wherein in response to detecting that the read errors are not localized to the block of the NVM, transmit a signal to a host that the read errors are uncorrectable.

12. The system of claim 9, wherein the block comprises 256 pages.

13. The system of claim 12, wherein the NVM is a dual-die dual-plane device, and the last two pages of the block are parity pages.

14. The system of claim 12, wherein the NVM is a dual-die dual-plane device, and the last two stripes of the band are parity stripes.