CAM bit error recovery
First Claim
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1. A method for content addressable memory (CAM) error recovery, comprising:
- detecting an error in an entry of a CAM;
identifying an address of the entry in the CAM;
copying data from the address in a backup random access memory (RAM) into the entry of the CAM to obtain a corrected CAM;
clearing a results (first in first out) FIFO structure based on detecting the error;
performing, using the corrected CAM, a match request stored in a replay FIFO structure to obtain a revised result; and
storing the revised result in the results FIFO structure.
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Abstract
A method for content addressable memory (CAM) error recovery that includes detecting an error in an entry of a CAM, identifying an address of the entry in the CAM, copying data from the address in the backup random access memory (RAM) into the entry of the CAM to obtain a corrected CAM, clearing a results (first in first out) FIFO structure based on detecting the error, performing, using the corrected CAM, a match request stored in a replay FIFO structure to obtain a revised result, and storing the revised result in the results FIFO structure.
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Citations
20 Claims
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1. A method for content addressable memory (CAM) error recovery, comprising:
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detecting an error in an entry of a CAM; identifying an address of the entry in the CAM; copying data from the address in a backup random access memory (RAM) into the entry of the CAM to obtain a corrected CAM; clearing a results (first in first out) FIFO structure based on detecting the error; performing, using the corrected CAM, a match request stored in a replay FIFO structure to obtain a revised result; and storing the revised result in the results FIFO structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A content addressable memory (CAM) system for error recovery, comprising:
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a CAM comprising a plurality of entries for storing data; a backup random access memory (RAM) operatively connected to the CAM, and for storing a copy of data stored in the plurality of entries of the CAM; a replay first in first out (FIFO) structure operatively connected to the CAM, and for storing a plurality of match requests; a results FIFO structure operatively connected to the CAM, and for storing a plurality of results of the plurality of match requests; and a master state machine operatively connected to the CAM, the results FIFO structure, the replay FIFO structure, and the backup RAM, and configured to; receive notification of an error in an entry of the plurality of entries, initiate copying of data from the backup RAM into the entry of the CAM to obtain a corrected CAM, clear the results FIFO structure based on detecting the error, and initiate performing, using the corrected CAM and the replay FIFO structure, a match request of the plurality of match requests. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A chip comprising:
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a content addressable memory (CAM) comprising a plurality of entries for storing data; a backup random access memory (RAM) physically connected to the CAM, and for storing a copy of data stored in the plurality of entries of the CAM; a replay first in first out (FIFO) structure physically connected to the CAM, and for storing a plurality of match requests; a results FIFO structure physically connected to the CAM, and for storing a plurality of results of the plurality of match requests; and a master state machine physically connected to the CAM, the results FIFO structure, the replay FIFO structure, and the backup RAM, and configured to; receive notification of an error in an entry of the plurality of entries, initiate copying of data from the backup RAM into the entry of the CAM to obtain a corrected CAM, clear the results FIFO structure based on detecting the error, and initiate performing, using the corrected CAM and the replay FIFO structure, a match request of the plurality of match requests. - View Dependent Claims (19, 20)
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Specification