Sense amplifier circuitry for resistive type memory

• US 9,070,424 B2
• Filed: 06/29/2012
• Issued: 06/30/2015
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Youn, YongSik, Cha, Sooho, Kim, Chan-kyung
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Bashar, Mohammed A
• Application Number:
  US13/538,869
• Publication Number:
  US 20140003124A1
• Time in Patent Office: 1,096 Days
• Field of Search: 365/148, 365/210, 365/207, 365/233.1, 365/230.06
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2013/0042 Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

Example embodiments include a resistive type memory sense amplifier circuit including differential output terminals, first and second input terminals, a pre-charge section, and other components arranged so that current is re-used during at least a “set” or “amplification” stage of the sense amplifier circuit, thereby reducing overall current consumption of the circuit, and improving noise immunity. A voltage level of a high-impedance output terminal is caused to swing in response to a delta average current between a reference line current and a bit line current. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit. Also disclosed is a current mirror circuit, which can be used in conjunction with the disclosed sense amplifier circuit. In yet another embodiment, a sense amplifier circuit includes the capability of read/re-write operation.

Claims

1. A resistive type memory sense amplifier circuit, comprising:

a first differential output terminal configured to output a first output signal;

a second differential output terminal configured to output a second output signal opposite the first output signal;

a first input terminal coupled to a bit line associated with a resistive type memory cell;

a second input terminal coupled to a reference line associated with a reference memory cell;

a first transistor coupled to the second input terminal and to the first differential output terminal, the first transistor being configured to conduct a reference line current;

a second transistor coupled to the first differential output terminal and arranged in series with the first transistor, the second transistor being configured to conduct a bit line current;

a pre-charge section coupled to an intermediate power supply voltage node, the intermediate power supply voltage node having a voltage level between a power supply voltage and a ground voltage, the pre-charge section including;

a first pre-charge transistor coupled to the first differential output terminal and to the intermediate power supply voltage node; and

a second pre-charge transistor coupled to the second differential output terminal and the intermediate power supply voltage node,

wherein the pre-charge section is configured to operate during a pre-charge stage of the sense amplifier circuit, and

wherein a voltage level of the first differential output terminal is configured to swing responsive to a delta average current between the reference line current and the bit line current.

2. The resistive type memory sense amplifier circuit of claim 1, wherein the bit line is configured to re-use at least some of the reference line current associated with the reference line.

3. The resistive type memory sense amplifier circuit of claim 1, wherein:

a drain of the second transistor is directly coupled to the first differential output terminal and to a drain of the first transistor;

a source of the second transistor is coupled to the bit line associated with the memory cell;

the first differential output terminal comprises a high-impedance output terminal; and

the voltage level of the high-impedance output terminal is configured to swing responsive to an amplification stage of the sense amplifier circuit.

4. The resistive type memory sense amplifier circuit of claim 1, wherein:

the first pre-charge transistor is configured to receive a pre-charge control signal and to pre-charge at least the bit line associated with the memory cell and the reference line during the pre-charge stage of the sense amplifier circuit responsive to the pre-charge control signal; and

the second pre-charge transistor is configured to receive the pre-charge control signal and to pre-charge at least a parasitic capacitance associated with the second differential output terminal during the pre-charge stage of the sense amplifier circuit responsive to the pre-charge control signal.

5. The resistive type memory sense amplifier circuit of claim 1, further comprising a cross-coupled latch circuit coupled to the first and second differential output terminals, wherein the cross-coupled latch circuit comprises:

a first latch enable transistor coupled to a power supply voltage node and configured to enable a latch stage of the sense amplifier circuit responsive to a first latch control signal;

a first latch transistor coupled to the first latch enable transistor and to the first differential output terminal;

a second latch transistor coupled to the first latch enable transistor and to the second differential output terminal;

a second latch enable transistor coupled to a ground voltage node and configured to enable the latch stage of the sense amplifier circuit responsive to a second latch control signal;

a third latch transistor coupled to the second latch enable transistor and to the first differential output terminal; and

a fourth latch transistor coupled to the second latch enable transistor and to the second differential output terminal,

wherein the latch transistors are configured to latch, based on positive feedback, a logical value “

0”

or logical value “

1”

at the first or second differential output terminals, respectively, depending on a bit value stored in the resistive type memory cell, and responsive to the first and second latch enable transistors being turned on by the first and second latch control signals, respectively, during the latch stage.

6. The resistive type memory sense amplifier circuit of claim 5, wherein:

the first latch enable transistor is a PMOS type transistor;

the second latch enable transistor is an NMOS type transistor;

the first and second latch transistors are each a PMOS type transistor; and

the third and fourth latch transistors are each an NMOS type transistor.

7. The resistive type memory sense amplifier circuit of claim 5, wherein:

a source of the first latch transistor is directly coupled to a drain of the first latch enable transistor;

a source of the second latch transistor is directly coupled to a drain of the first latch enable transistor;

a source of the third latch transistor is directly coupled to a drain of the second latch enable transistor; and

a source of the fourth latch transistor is directly coupled to the drain of the second latch enable transistor.

8. The resistive type memory sense amplifier circuit of claim 5, wherein:

a gate of the first latch transistor is coupled to the second differential output terminal;

a gate of the second latch transistor is coupled to the first differential output terminal;

a gate of the third latch transistor is coupled to the second differential output terminal; and

a gate of the fourth latch transistor is coupled to the first differential output terminal.

9. The resistive type memory sense amplifier circuit of claim 5, wherein:

a drain of each of the first and third latch transistors is coupled to the first differential output terminal; and

a drain of each of the second and fourth latch transistors is coupled to the second differential output terminal.

10. The resistive type memory sense amplifier circuit of claim 1, wherein the resistive type memory cell includes at least one of a spin transfer torque (STT) magnetoresistive random-access memory (MRAM) cell, an MRAM cell, a memristor RAM cell, an ReRAM cell, or a CBRAM cell.

11. The resistive type memory sense amplifier circuit of claim 1, wherein the resistive type memory cell is a spin transfer torque (STT) magnetoresistive random-access memory (MRAM) cell.

12. The resistive type memory sense amplifier circuit of claim 1, further comprising a source line coupled to the memory cell, wherein:

the source line is coupled to one of a power supply voltage node or a ground voltage node;

when the source line is coupled to the ground voltage node, the sense amplifier circuit includes a first transistor configuration; and

when the source line is coupled to the power supply voltage node, the sense amplifier circuit includes a second transistor configuration that is swapped relative to the first transistor configuration.

13. A resistive type memory sense amplifier circuit, comprising:

a first differential output terminal configured to output a first output signal;

a second differential output terminal configured to output a second output signal opposite the first output signal;

a first input terminal coupled to a bit line associated with a resistive type memory cell;

a second input terminal coupled to a reference line associated with a reference memory cell;

a first transistor coupled to the second input terminal and to the first differential output terminal, the first transistor being configured to conduct a reference line current;

a second transistor coupled to the first differential output terminal and arranged in series with the first transistor, the second transistor being configured to conduct a bit line current; and

wherein a voltage level of the first differential output terminal is configured to swing responsive to a delta average current between the reference line current and the bit line current,

wherein;

the first transistor is a PMOS type transistor; and

the second transistor is an NMOS type transistor.

14. The resistive type memory sense amplifier circuit of claim 13, wherein the bit line is configured to re-use at least some of the reference line current associated with the reference line.

15. The resistive type memory sense amplifier circuit of claim 13, wherein:

a drain of the second transistor is directly coupled to the first differential output terminal and to a drain of the first transistor;

a source of the second transistor is coupled to the bit line associated with the memory cell;

the first differential output terminal comprises a high-impedance output terminal; and

the voltage level of the high-impedance output terminal is configured to swing responsive to an amplification stage of the sense amplifier circuit.

16. The resistive type memory sense amplifier circuit of claim 13, further comprising a pre-charge section coupled to an intermediate power supply voltage node, the intermediate power supply voltage node having a voltage level between a power supply voltage and a ground voltage, the pre-charge section including:

a first pre-charge transistor coupled to the first differential output terminal and to the intermediate power supply voltage node; and

a second pre-charge transistor coupled to the second differential output terminal and the intermediate power supply voltage node,

wherein the pre-charge section is configured to operate during a pre-charge stage of the sense amplifier circuit.

17. The resistive type memory sense amplifier circuit of claim 13, wherein the resistive type memory cell includes at least one of a spin transfer torque (STT) magnetoresistive random-access memory (MRAM) cell, an MRAM cell, a memristor RAM cell, an ReRAM cell, or a CBRAM cell.

18. The resistive type memory sense amplifier circuit of claim 13, wherein the resistive type memory cell is a spin transfer torque (STT) magnetoresistive random-access memory (MRAM) cell.

19. The resistive type memory sense amplifier circuit of claim 13, further comprising a source line coupled to the memory cell, wherein:

the source line is coupled to one of a power supply voltage node or a ground voltage node;

when the source line is coupled to the ground voltage node, the sense amplifier circuit includes a first transistor configuration; and

when the source line is coupled to the power supply voltage node, the sense amplifier circuit includes a second transistor configuration that is swapped relative to the first transistor configuration.

20. A method for sensing bit information stored in a resistive type memory, the method comprising:

in a pre-charge stage of a sense amplifier circuit, pre-charging, by a pre-charge section, at least a bit line and a reference line;

in an amplification stage of the sense amplifier circuit, causing a reference line current to flow through the reference line and a bit line current to flow through the bit line;

in the amplification stage of the sense amplifier circuit, causing a voltage swing at a first differential output terminal responsive to a delta average current between the reference line current and the bit line current; and

in a latch stage of the sense amplifier circuit, latching, by a latch circuit, a logical value “

0”

or logical value “

1”

at the first differential output terminal or a second differential output terminal, respectively, using positive feedback of the latch circuit.

21. The method of claim 20, wherein causing the bit line current to flow through the bit line includes re-using at least some of the reference line current flowing through the reference line.

22. The method of claim 20, wherein:

the first differential output terminal comprises a high-impedance output terminal; and

causing the voltage swing at the high-impedance output terminal includes multiplying, by the delta average current, a parasitic impedance associated with the high-impedance output terminal.

23. The method of claim 20, wherein:

pre-charging, by the pre-charge section, includes pre-charging at least the bit line and the reference line using an intermediate power supply voltage node having a voltage level between a power supply voltage and a ground voltage.

24. A resistive type memory sense amplifier circuit, comprising:

a first input/output terminal configured to output a first output signal, the first input/output terminal being coupled to a reference line associated with a reference memory cell and to a bit line associated with a resistive type memory cell, the reference line and the bit line being configured to conduct a reference line current;

a second input/output terminal configured to output a second output signal opposite the first output signal;

a transistor coupled to the first input/output terminal and to the reference line, the transistor being configured to conduct the reference line current; and

a cross-coupled latch circuit coupled to the first and second input/output terminals, to a positive power supply voltage node, and to a negative power supply voltage node, wherein;

the latch circuit is configured to latch, based on positive feedback, a logical value “

0”

or logical value “

1”

at the first or second input/output terminals, respectively, depending on a bit value stored in the resistive type memory cell;

the logical value “

1”

corresponds to one of a positive voltage level of the positive power supply voltage node or a negative voltage level of the negative power supply voltage node;

the logical value “

0”

corresponds to the other of the positive voltage level of the positive power supply voltage node or the negative voltage level of the negative power supply voltage node; and

the resistive type memory cell is configured to be re-written by the latched positive voltage level or the latched negative voltage level, and

wherein a voltage level of the first input/output terminal is configured to swing responsive to the reference line current multiplied by a resistance associated with the resistive type memory cell.