Contact structure and forming method

• US 9,070,447 B2
• Filed: 07/07/2014
• Issued: 06/30/2015
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Shih-Hung
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US14/325,069
• Publication Number:
  US 20150085579A1
• Time in Patent Office: 358 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second buffer layer under the first sub stack. An upper layer of the first sub stack is exposed through a set of vias by first and second etching processes. The first etching process forms a first set of etch vias through the second sub stack and stops at or in the first buffer layer. The second etching process etches through the first buffer layer to the upper layer of the first sub stack. A third etching process etches through the first set of etch vias, through the first sub stack and stops at or in the second buffer layer. A fourth etching process and etches through the second buffer layer.

Claims

1. A method for forming vias within a stack of layers comprising:

forming a stack of alternating active layers and insulating layers, comprising;

forming a first sub stack comprising N active layers separated by insulating layers;

forming a second sub stack over the first sub stack, the second sub stack comprising M active layers separated by insulating layers; and

forming a first buffer layer between the first and second sub stacks and a second buffer layer under the first sub stack;

exposing an upper layer of the first sub stack through a set of vias by;

etching, using a first etching process to form a first set of etch vias through the second sub stack and stopping at or in the first buffer layer, and then

etching, using a second etching process through the first buffer layer to the upper layer of the first sub stack; and

etching through the first sub stack by;

etching, using a third etching process through the first set of etch vias through the first sub stack and stopping at or in the second buffer layer, and then

etching, using a fourth etching process through the second buffer layer.

2. The method of claim 1, further comprising:

etching through the vias to create a stairstep structure of landing areas on the active layers of the first sub stack and the second sub stack; and

forming interlayer conductors extending to the landing areas.

3. The method of claim 2, wherein the etching to create a stairstep structure comprises using a single etching process to create landing areas on an integer multiple of N layers, the integer multiple being at least 2.

4. The method of claim 1, wherein the first buffer layer has an etching time greater than the etching time of an insulating layer of the second sub stack for their respective second and first etching processes.

5. The method of claim 1, wherein the first buffer layer (1) is made of the same material as the insulating layers of the first sub stack but has a different thickness than an insulating layer of the first sub stack, or (2) has a different material composition than the insulating layers of the first sub stack, or (3), both (1) and (2).

6. The method of claim 1, wherein the first buffer layer has a thickness at least 1.5 times greater than the thickness of an active layer in the first sub stack.

7. The method of claim 1, wherein the first sub stack is characterized by a first spatial period N1, and the second sub stack is characterized by a second spatial period N2, where N1 is equal to N2.

8. The method of claim 1, further comprising:

creating an etch mask over the second sub stack, the etch mask having etch mask openings; and

wherein;

the upper layer exposing step is carried out through the etch mask openings.

9. The method of claim 1, wherein the first and second sub stack forming steps are carried out so that the upper layer of each is thicker than at least one of the active and insulating layers of the corresponding sub stack.