Mismatch error reduction method and system for STT MRAM

• US 9,070,466 B2
• Filed: 09/06/2012
• Issued: 06/30/2015
• Est. Priority Date: 09/06/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Jefremow, Mihail, Allers, Wolf, Otterstedt, Jan, Peters, Christian, Kern, Thomas
• Primary Examiner(s): King, Douglas
• Application Number:
  US13/605,693
• Publication Number:
  US 20140063923A1
• Time in Patent Office: 1,027 Days
• Field of Search: 365/189.07, 365/189.09, 365/158, 365/203
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods

Abstract

The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.

Claims

1. A method for reducing mismatch error for a sense amplifier for memory cells, comprising:

during a precharge phase, averaging a cell current from a memory cell and a reference current from a reference source and flowing the averaged current through a first mirror transistor and a second mirror transistor of the sense amplifier;

during the precharge phase, storing a current mismatch between a sense path and a reference path of the sense amplifier on a capacitor between gate terminals of a first mirror transistor and a second mirror transistor that reside in the sense path and the reference path, respectively; and

during a sensing phase, conducting only the cell current through the first mirror transistor in the sense path and solely the reference current through the second mirror transistor in the reference path.

2. The method of claim 1, wherein the first mirror transistor and the second mirror transistor are diode connected transistors

3. The method of claim 1, wherein a difference between a gate voltage of the first mirror transistor and a gate voltage of the second mirror transistor is stored on the capacitor between the gates of the first and second mirror transistors and reflects the current mismatch.

4. The method of claim 1, wherein averaging the cell current and the reference current is done before flowing through a first bitline transistor in the sense path and a second bitline transistor in the reference path, respectively.

5. The method of claim 1, wherein averaging the cell current from the memory cell and the reference current from the reference source is used during the precharge phase to measure and store the current mismatch between the sense and the reference paths.

6. The method of claim 1, wherein only the reference current flows through the second mirror transistor during the sensing phase.

7. The method of claim 1, wherein a gate voltage of the first mirror transistor is shifted by a voltage difference between gates of the first and second mirror transistors previously stored on the capacitor during the sensing phase.

8. The method of claim 1, wherein the current mismatch is canceled out during the precharge phase.

9. The method of claim 1, wherein the memory cell is an STT MRAM cell.

10. A system for sensing a memory cell, comprising:

a first mirror transistor in a sense path and a second mirror transistor in a reference path; and

a capacitor coupled between gate terminals of the first mirror transistor and the second mirror transistor;

wherein during a precharge phase a current mismatch between the first mirror transistor and the second mirror transistor is stored on the capacitor, and a cell current of the memory cell in the sense path and a reference current in the reference path are averaged before flowing through the first and second mirror transistors.

11. The system of claim 10, wherein the current mismatch is stored on the capacitor as a voltage during the precharge phase.

12. The system of claim 10, wherein averaging the cell current and the reference current is used for the precharge phase to measure and store the current mismatch between the sense path and the reference path.

13. The system of claim 10, wherein a difference between a gate voltage of the first mirror transistor and a gate voltage of the second mirror transistor is stored on the capacitor and reflects the current mismatch during the precharge phase.

14. The system of claim 10, wherein only the reference current flows through the second mirror transistor during a sensing phase that follows the pre-charge phase.

15. The system of claim 10, wherein a gate voltage of the first mirror transistor during a sensing phase that follows the pre-charge phase is shifted by a differential voltage that represents the current mismatch stored on the capacitor.

16. The system of claim 10, wherein the current flowing through the first mirror transistor in the sense path during the sensing phase that follows the precharge phase is substantially equal to the reference current through the second mirror transistor in the reference path.

17. The system of claim 10, wherein the current mismatch is canceled out during the precharge phase.

18. The system of claim 10, wherein the memory cell is an STT MRAM cell.

19. A method for reducing mismatch error for a sense amplifier for memory cells, the method comprising:

providing an average current flowing through both a first mirror transistor in a sense path and a second mirror transistor in a reference path during a precharge phase;

storing a current mismatch between the sense path and the reference path on a capacitor coupled to gates of the first mirror transistor and the second mirror transistor; and

providing a cell current through the first mirror transistor during a sensing phase that follows the precharge phase and a reference current flowing through the second mirror transistor.

20. The method of claim 19, wherein the first mirror transistor and the second mirror transistor are diode connected transistors.

21. The method of claim 19, wherein a difference between a gate voltage of the first mirror transistor and a gate voltage of the second mirror transistor is stored on the capacitor coupled between the gates of the first and second mirror transistors.

22. The method of claim 19, wherein providing an average current further comprises combining a cell current from a memory cell in the sense path and a reference current from a reference source in the reference path.

23. The method of claim 19, wherein combining the cell current and the reference current is done before providing a current through a first bitline transistor in the sense path and a second bitline transistor in the reference path.

24. The method of claim 19, wherein a gate voltage of the first mirror transistor is shifted in the sensing phase by a voltage difference between the gates of the first and second mirror transistors previously stored on the capacitor in the precharge phase.

25. The method of claim 19, wherein the current through the first mirror transistor during the sensing phase is independent of the current mismatch.

26. The method of claim 19, wherein the memory cell is an STT MRAM cell.

27. A system for sensing a memory cell, comprising:

a first mirror transistor in a sense path and a second mirror transistor in a reference path;

a capacitor coupled between gate terminal of the first mirror transistor and the second mirror transistor for storing a current mismatch between the first mirror transistor and the second mirror transistor in a precharge phase; and

a reference source configured to provide a reference current,

wherein a cell current from the memory cell and the reference current from the reference source are combined to provide an average current flowing through the first and second mirror transistors during the precharge phase and wherein the average current is used to measure and store the current mismatch between the sense and the reference paths on the capacitor; and

wherein the current mismatch is canceled out during the precharge phase.

28. The system of claim 27, wherein the current mismatch is stored on the capacitor as a voltage during the precharge phase.

29. The system of claim 27, wherein a difference between a gate voltage of the first mirror transistor and a gate voltage of the second mirror transistor is stored on the capacitor in the precharge phase.

30. The system of claim 27, wherein only the reference current flows through the second mirror transistor during a sensing phase that follows the precharge phase.

31. The system of claim 27, wherein a gate voltage of the first mirror transistor during a sensing phase that follows the precharge phase is shifted by a differential voltage stored on the capacitor that reflects the current mismatch.

32. The system of claim 27, wherein the current flowing through the first mirror transistor is independent of the current mirror mismatch in the sensing phase.

33. The system of claim 27, wherein the memory cell is an STT MRAM cell.