Bit interleaved low voltage static random access memory (SRAM) and related methods

• US 9,070,477 B1
• Filed: 12/12/2013
• Issued: 06/30/2015
• Est. Priority Date: 12/12/2012
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Clark, Lawrence T.
• Primary Examiner(s): Norman, James G
• Application Number:
  US14/104,182
• Time in Patent Office: 565 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A method can include applying a device power supply voltage to an integrated circuit including a static random access memory (SRAM) with transistors having at least a first threshold voltage (Vt); applying an array power supply voltage to cells of the SRAM that is near or below Vt; and in a write operation, reading data from at least a first group of the cells that is interleaved with a second group of the cells, and applying the read data to the bit lines of the first group of cells, while write data is applied to the bit lines of the second group of cells.

Claims

1. A method, comprising:

applying a device power supply voltage to an integrated circuit including a static random access memory (SRAM) with transistors having at least a first threshold voltage (Vt);

applying an array power supply voltage to cells of the SRAM that is near or below Vt; and

in a write operation,

reading data from at least a first group of the cells that is interleaved with a second group of the cells, and

applying the read data to the bit lines of the first group of cells, while write data is applied to the bit lines of the second group of cells.

2. The method of claim 1, wherein:

the array power supply voltage is less than Vt.

3. The method of claim 1, wherein:

the array power supply voltage is no more than 250 mV greater than Vt.

4. The method of claim 3, wherein:

the array power supply voltage is no more than 100 mV greater than Vt.

5. The method of claim 1, further including:

body biasing the transistors to set their threshold voltage to Vt.

6. The method of claim 1, further including:

dynamically body biasing the transistors to change their threshold voltages between Vt and another value.

7. The method of claim 1, wherein:

the cells comprise eight transistor SRAM cells.

8. An integrated circuit, comprising:

at least one static random access memory (SRAM) comprising cells arranged into interleaved groups configured to receive an array power supply voltage; and

write circuits configured to apply data read from one of the interleaved groups to bit lines of the interleaved group and while write data is applied to bit lines of the other of the interleaved groups;

wherein

the cells comprise transistors having at least a first threshold voltage (Vt), and the array power supply voltage is near or below Vt.

9. The integrated circuit of claim 8, wherein:

the array power supply voltage is less than Vt.

10. The integrated circuit of claim 8, wherein:

the array power supply voltage is no more than 250 mV greater than Vt.

11. The integrated circuit of claim 8, wherein:

the array power supply voltage is no more than 100 mV greater than Vt.

12. The integrated circuit of claim 8, further including:

body biasing circuits configured to generate a body bias voltage to the transistors that sets their threshold voltage to Vt.

13. The integrated circuit of claim 8, wherein:

the cells comprise eight transistor SRAM cells.

14. An integrated circuit, comprising:

a plurality of static random access memory (SRAM) cells arranged into interleaved groups, the plurality of SRAM cells comprising columns, the plurality of SRAM cells coupled to receive an array power supply voltage, each SRAM cell including

a latch circuit coupled to at least one write bit line by a first access device coupled to a write word line, the latch circuits comprising transistors having at least a first threshold voltage (Vt), and

a read circuit configured to establish a voltage on a read bit line in response to activation of a corresponding read word line;

write circuits configured to apply data read from one of the interleaved groups to write bit lines of the interleaved group while applying write data to write bit lines of the other of the interleaved groups;

wherein

the array power supply voltage is near or below Vt.

15. The integrated circuit of claim 14, wherein:

the array power supply voltage is less than Vt.

16. The integrated circuit of claim 14, wherein:

the array power supply voltage is no more than 250 mV greater than Vt.

17. The integrated circuit of claim 14, wherein:

the write circuits each include a multiplexer (MUX) having one input coupled to a read bit line, another input coupled to receive a write data value, and an output coupled to a write bit line coupled to the same SRAM cells as the read bit line.

18. The integrated circuit of claim 14, wherein:

the SRAM cells comprise eight transistor (8-T) SRAM cells.

19. The integrated circuit of claim 14, further including:

the read circuit of at least two of the SRAM cell columns comprises a differential read circuit configured to establish complementary voltages on complementary read bit lines in response to activation of a corresponding read word line; and

a detect circuit configured to detect when the read bit lines have complementary values, wherein a write control signal is asserted after a complementary read value has been detected.

20. The integrated circuit of claim 14, further including:

body biasing circuits configured to apply a body bias voltage to the SRAM cells to establish the threshold voltage of Vt.