Internal current measurement for age measurements

• US 9,070,481 B1
• Filed: 06/06/2014
• Issued: 06/30/2015
• Est. Priority Date: 05/30/2014
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Higgins, James M., Mak, Alexander Kwok-Tung, Ellis, Robert W.
• Primary Examiner(s): Trimmings, John P
• Application Number:
  US14/298,854
• Time in Patent Office: 389 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/3034 where the computing system component is a storage system, e.g. DASD based or network based digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: G06F 11/3089 Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents software debugging using additional hardware using a specific debug interface G06F11/3656; performance evaluation by tracing or monitoring G06F11/3466
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50008 of impedance

Abstract

A method of operation in a non-volatile memory device, including executing a memory operation with respect to a portion of a non-volatile memory device, and measuring a current corresponding to current drawn by at least the portion of the non-volatile memory device during the memory operation. An age metric is determined for at least the portion of the non-volatile memory device based on age criteria including a characteristic of the measured current. In accordance with a determination that the age metric satisfies one or more predefined threshold criteria, one or more configuration parameters associated with the non-volatile memory device are adjusted. After the adjusting, data is read from and data to the portion of the non-volatile memory device according to the one or more adjusted configuration parameters.

Claims

1. A method of operation in a non-volatile memory device, the method comprising:

executing a memory operation in a portion of the non-volatile memory device;

measuring a current corresponding to total current drawn by at least the portion of the non-volatile memory device over the duration of a sampling window for the memory operation;

determining an age metric for at least the portion of the non-volatile memory device based on the measured current;

in accordance with a determination that the age metric satisfies one or more predefined threshold criteria, adjusting one or more configuration parameters associated with at least the portion of the non-volatile memory device; and

after the adjusting, reading data from and writing data to the portion of the non-volatile memory device according to the one or more adjusted configuration parameters.

2. The method of claim 1, wherein the one or more adjusted configuration parameters include at least one of:

a storage density of the non-volatile memory device or the portion of the non-volatile memory device;

an error correction code (ECC) strength; and

a wear leveling setting.

3. The method of claim 1, wherein the age metric is a numerical metric having a value that varies with changes in the measured current.

4. The method of claim 1, wherein the duration of the sampling window comprises the duration of the memory operation.

5. The method of claim 1, wherein measuring the current is from a physical location internal to the non-volatile memory device.

6. The method of claim 1, wherein measuring the current includes measuring the current drawn across one or more bit lines corresponding to the portion of the non-volatile memory device.

7. The method of claim 1, wherein the age metric is a numerical metric having a value that varies with changes in the measured current, and determining the age metric is based on the measured current and one or more additional factors selected from the group consisting of:

a program-erase (PE) cycle count corresponding to a number of PE cycles performed on the portion of the non-volatile memory device;

a number of erase loops required for successfully executing the memory operation, wherein the memory operation is an erase operation; and

a measured bit error rate (BER) of the portion of the non-volatile memory device.

8. The method of claim 1, wherein the non-volatile memory device comprises one or more three-dimensional (3D) memory devices and circuitry associated with operation of memory elements in the one or more 3D memory devices.

9. The method of claim 8, wherein the circuitry and one or more memory elements in a respective 3D memory device, of the one or more 3D memory devices, are on the same substrate.

10. A memory system, comprising:

a plurality of non-volatile memory devices;

a plurality of memory controllers;

a processor; and

memory for storing one or more programs for execution by the processor, the one or more programs including instructions for performing operations comprising;

initiating execution of a memory operation in a portion of a non-volatile memory device;

measuring a current corresponding to total current drawn by at least the portion of the non-volatile memory device over the duration of a sampling window for the memory operation;

determining an age metric for at least the portion of the non-volatile memory device based on the measured current;

in accordance with a determination that the age metric satisfies one or more predefined threshold criteria, adjusting one or more configuration parameters associated with at least the portion of the non-volatile memory device; and

after the adjusting, reading data from and writing data to the portion of the non-volatile memory device according to the one or more adjusted configuration parameters.

11. The memory system of claim 10, wherein the one or more adjusted configuration parameters include at least one of:

a storage density of the non-volatile memory device or the portion of the non-volatile memory device;

an error correction code (ECC) strength; and

a wear leveling setting.

12. The memory system of claim 10, wherein the age metric is a numerical metric having a value that varies with changes in the measured current.

13. The memory system of claim 10, wherein the duration of the sampling window comprises the duration of the memory operation.

14. The memory system of claim 10, wherein measuring the current is from a physical location internal to the non-volatile memory device.

15. The memory system of claim 10, wherein measuring the current includes measuring the current drawn across one or more bit lines corresponding to the portion of the non-volatile memory device.

16. The memory system of claim 10, wherein the age metric is a numerical metric having a value that varies with changes in the measured current, and determining the age metric is based on the measured current and one or more additional factors selected from the group consisting of:

a program-erase (PE) cycle count corresponding to a number of PE cycles performed on the portion of the non-volatile memory device;

a number of erase loops required for successfully executing the memory operation, wherein the memory operation is an erase operation; and

a measured bit error rate (BER) of the portion of the non-volatile memory device.

17. The memory system of claim 10, wherein the non-volatile memory device comprises one or more three-dimensional (3D) memory devices and circuitry associated with operation of memory elements in the one or more 3D memory devices.

18. The memory system of claim 17, wherein the circuitry and one or more memory elements in a respective 3D memory device, of the one or more 3D memory devices, are on the same substrate.

19. A non-transitory computer readable storage medium, storing one or more programs for execution by one or more processors, the one or more programs including instructions for performing operations comprising:

initiating execution of a memory operation in a portion of a non-volatile memory device;

measuring a current corresponding to total current drawn by at least the portion of the non-volatile memory device over the duration of a sampling window for the memory operation;

determining an age metric for at least the portion of the non-volatile memory device based on the measured current;

in accordance with a determination that the age metric satisfies one or more predefined threshold criteria, adjusting one or more configuration parameters associated with at least the portion of the non-volatile memory device; and

after the adjusting, reading data from and writing data to the portion of the non-volatile memory device according to the one or more adjusted configuration parameters.

20. The non-transitory computer readable storage medium of 19, wherein the one or more adjusted configuration parameters include at least one of:

a storage density of the non-volatile memory device or the portion of the non-volatile memory device;

an error correction code (ECC) strength; and

a wear leveling setting.

21. The non-transitory computer readable storage medium of 19, wherein the age metric is a numerical metric having a value that varies with change in the measured current.

22. The non-transitory computer readable storage medium of 19, wherein the duration of the sampling window comprises the duration of the memory operation.

23. The non-transitory computer readable storage medium of 19, wherein measuring the current is from a physical location internal to the non-volatile memory device.

24. The non-transitory computer readable storage medium of 19, wherein measuring the current includes measuring the current drawn across one or more bit lines corresponding to the portion of the non-volatile memory device.

25. The non-transitory computer readable storage medium of 19, wherein the age metric is a numerical metric having a value that varies with changes in the measured current, and determining the age metric is based on the measured current and one or more additional factors selected from the group consisting of:

a program-erase (PE) cycle count corresponding to a number of PE cycles performed on the portion of the non-volatile memory device;

a number of erase loops required for successfully executing the memory operation, wherein the memory operation is an erase operation; and

a measured bit error rate (BER) of the portion of the non-volatile memory device.

26. The non-transitory computer readable storage medium of 19, wherein the non-volatile memory device comprises one or more three-dimensional (3D) memory devices and circuitry associated with operation of memory elements in the one or more 3D memory devices.

27. The non-transitory computer readable storage medium of 26, wherein the circuitry and one or more memory elements in a respective 3D memory device, of the one or more 3D memory devices, are on the same substrate.