Nitride semiconductor wafer for a high-electron-mobility transistor and its use

• US 9,070,619 B2
• Filed: 08/08/2013
• Issued: 06/30/2015
• Est. Priority Date: 09/03/2012
• Status: Active Grant

• Current Assignee: Sumitomo Chemical Company Limited
• Original Assignee: Hitachi Metals (Thailand) Ltd.
• Inventors: Tsuchiya, Tadayoshi
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Gebreyesus, Yosef
• Application Number:
  US13/962,812
• Publication Number:
  US 20140061665A1
• Time in Patent Office: 691 Days
• Field of Search: 257/11, 257/189, 257/190, 257/191, 257/194, 257/615, 257/E33.023, 257/E33.025, 257/E33.028, 257/E29.089, 257/E21.097, 257/E21.108, 257/E21.127
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/02581 Transition metal or rare earth elements
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material

Abstract

A nitride semiconductor wafer includes a substrate, and a buffer layer formed on the substrate and including an alternating layer of Al_xGa_1-xN (0≦x≦0.05) and Al_yGa_1-yN (0<y≦1 and x<y) layers. Only the Al_yGa_1-yN layer in the alternating layer is doped with an acceptor.

Claims

1. A high-electron-mobility transistor nitride semiconductor wafer, comprising:

a substrate;

a buffer layer formed on the substrate and comprising an alternating layer of an Al_xGa_1-xN (0≦

x≦

0.05) layer and an Al_yGa_1-yN (0<

y≦

1 and x<

y) layer;

a nitride semiconductor channel layer formed on the buffer layer; and

a nitride semiconductor barrier layer formed on the channel layer,

wherein only the Al_yGa_1-yN layer of the alternating layer is doped with an acceptor.

2. The high-electron-mobility transistor nitride semiconductor wafer according to claim 1, wherein a sheet concentration Ns of the acceptor in an uppermost Al_yGa_1-yN layer among the Al_yGa_1-yN layer of the alternating layer is not more than 2×

10¹³ cm<sup>−

2</sup>.

3. The high-electron-mobility transistor nitride semiconductor wafer according to claim 2, wherein an Al composition y of the uppermost Al_yGa_1-yN layer is 0<

y≦

0.4, and

wherein the sheet concentration Ns is 5×

10¹³·

y<

Ns≦

2×

10¹³ cm<sup>−

2</sup>.

4. The high-electron-mobility transistor nitride semiconductor wafer according to claim 1, wherein the acceptor comprises one of iron (Fe), carbon (C), and zinc (Zn).

5. The high-electron-mobility transistor nitride semiconductor wafer according to claim 1, wherein an Al composition x of the Al_xGa_1-xN layer is x=0.

6. The high-electron-mobility transistor nitride semiconductor wafer according to claim 1, wherein an Al composition y and a sheet concentration Ns per layer are each equal in the Al_yGa_1-yN layer of the alternating layer.

7. The high-electron-mobility transistor nitride semiconductor wafer according to claim 1, wherein the Al_xGa_1-xN layer of the alternating layer is not doped with the acceptor.

9. The high-electron-mobility transistor nitride semiconductor wafer according to claim 1, further comprising:

a source electrode, a drain electrode, and a gate electrode formed on the barrier layer.

10. The high-electron-mobility transistor nitride semiconductor wafer according to claim 9, wherein the source electrode, the drain electrode, and the gate electrode are disposed on an upper surface of the barrier layer.

11. The high-electron-mobility transistor nitride semiconductor wafer according to claim 10, wherein the channel layer is disposed on a bottom surface of the barrier layer.

12. The high-electron-mobility transistor nitride semiconductor wafer according to claim 11, wherein a bottom surface of the channel layer is disposed on an upper surface of the buffer layer.

13. The high-electron-mobility transistor nitride semiconductor wafer according to claim 12, further comprising:

a GaN layer disposed on a bottom surface of the buffer layer.

14. The high-electron-mobility transistor nitride semiconductor wafer according to claim 13, wherein the GaN layer is further disposed on an upper surface of the substrate.

15. The high-electron-mobility transistor nitride semiconductor wafer according to claim 1, wherein the substrate comprises one of a non-doped GaN substrate and a Fe-doped GaN substrate.

16. The high-electron-mobility transistor nitride semiconductor wafer according to claim 15, wherein the channel layer comprises one of a GaN crystal and an InGaN crystal.

17. The high-electron-mobility transistor nitride semiconductor wafer according to claim 16, wherein the barrier layer comprises one of an AlGaN crystal and an InAlN crystal.

18. The high-electron-mobility transistor nitride semiconductor wafer according to claim 17, further comprising:

a source electrode, a drain electrode, and a gate electrode formed on the barrier layer,

wherein the source electrode and the drain electrode comprise a laminate of Ti/Al, and the gate electrode comprises a laminate of Pd/Au.

8. A nitride semiconductor wafer for using in a high-electron-mobility transistor, the nitride semiconductor wafer comprising:

a substrate;

a buffer layer formed on the substrate and comprising an alternating layer of an Al_xGa_1-xN (0≦

x≦

0.05) layer and an Al_yGa_1-yN (0<

y≦

1 and x<

y) layer;

a nitride semiconductor channel layer formed on the buffer layer; and

a nitride semiconductor barrier layer formed on the channel layer,

wherein only the Al_yGa_1-yN layer of the alternating layer is doped with an acceptor.

19. The nitride semiconductor wafer according to claim 8, further comprising:

a source electrode, a drain electrode, and a gate electrode formed on the barrier layer,

wherein the source electrode, the drain electrode, and the gate electrode are disposed on an upper surface of the barrier layer,

wherein the channel layer is disposed on a bottom surface of the barrier layer, and

wherein a bottom surface of the channel layer is disposed on an upper surface of the buffer layer.

20. The nitride semiconductor wafer according to claim 8, wherein the channel layer comprises one of a GaN crystal and an InGaN crystal,

wherein the barrier layer comprises one of an AlGaN crystal and an InAlN crystal,

wherein the nitride semiconductor wafer further comprises a source electrode, a drain electrode, and a gate electrode formed on the barrier layer, and

wherein the source electrode and the drain electrode comprise a laminate of Ti/Al, and the gate electrode comprises a laminate of Pd/Au.