Semiconductor device including polysilicon resistor and metal gate resistor and methods of fabricating thereof

• US 9,070,624 B2
• Filed: 12/16/2011
• Issued: 06/30/2015
• Est. Priority Date: 12/16/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Jian-Hao, Lu, Chia-Yu, Hsieh, Tung-Heng, Yu, Kuo-Feng, Hou, Chin-Shan, Lin, Hsien-Chin, Lin, Shyue-Shyh
• Primary Examiner(s): Fulk, Steven J
• Assistant Examiner(s): WARD, ERIC A
• Application Number:
  US13/328,875
• Publication Number:
  US 20130157452A1
• Time in Patent Office: 1,292 Days
• Field of Search: 438197-233, 438585-596
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.

Claims

1. A method, comprising:

forming a polysilicon layer on a semiconductor substrate;

etching the polysilicon layer to form a first region having a first height from a top surface of the semiconductor substrate and a second region having a second height from the top surface of the semiconductor substrate, wherein the second height is less than the first height;

forming a first gate structure on the semiconductor substrate, wherein the first gate structure is formed of the second region of the etched polysilicon layer and is disposed over an isolation region of the substrate;

forming a sacrificial gate structure on the semiconductor substrate adjacent the first gate structure, wherein the sacrificial gate structure is formed using the first region of the etched polysilicon layer and is disposed over an active region of the substrate adjacent the isolation region; and

forming a dielectric layer overlying the first gate structure and the sacrificial gate structure, wherein the dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness above a top surface of the sacrificial gate structure, wherein the second thickness is less than the first thickness;

after forming the dielectric layer, performing a planarization process on the dielectric layer to expose the top surface of the sacrificial gate structure, wherein after performing the planarization process a portion of the dielectric layer having a third thickness remains above the first gate structure;

after the planarization process, removing the sacrificial gate structure to form a trench;

forming a metal gate structure in the trench; and

forming a first contact to the first gate structure and forming a second contact to the metal gate structure.

2. The method of claim 1, further comprising:

depositing a layer of gate dielectric material underlying the layer of polysilicon.

3. The method of claim 1, further comprising:

doping the layer of polysilicon wherein the doping includes a germanium pre-amorphous implant (PAI).

4. The method of claim 3, wherein the doping is performed while a masking element is disposed on the first region of the layer of polysilicon and prior to the etching of the layer of polysilicon.

5. The method of claim 1, wherein the first thickness is greater than the second thickness by at least approximately 25 nanometers.

6. The method of claim 1, wherein the forming the first contact includes forming the first contact interfacing a top surface of the first gate structure and forming the second contact includes forming the second contact interfacing a top surface of the metal gate structure, wherein the top surface of the first gate structure has a first height above the top surface of the semiconductor substrate and the top surface of the metal gate structure has a second height above the top surface of the semiconductor substrate, wherein the second height is greater than the first height.

7. The method of claim 1, further comprising:

doping the polysilicon layer prior to the etching, wherein the doping includes performing a shallow implant of arsenic to form an arsenic-rich upper region and performing a deeper implant of boron in the polysilicon layer to form a boron-rich lower region; and

using the lower region as an etch-stop for the etching the polysilicon layer.

8. A method, comprising:

providing a substrate having a first surface;

forming a recess in an isolation region of the substrate, thereby providing a recessed region having a second surface of dielectric material spaced a distance from the first surface, wherein the recess is defined by a first sidewall edge of dielectric material and an opposing second sidewall edge of dielectric material, wherein first and second active regions having a top surface of the first surface interpose the first sidewall edge and second sidewall edge such that the recess having the second surface is disposed between the first and second active regions and on opposing sides of each of the first and second isolation features;

forming a polysilicon gate structure in the recess on the second surface and interposing the first and second active regions;

forming a first sacrificial gate structure on the first surface in the first active region;

forming a second sacrificial gate structure on the first surface in the isolation region and adjacent the second sidewall edge of the recess; and

forming a dielectric layer overlying the polysilicon gate structure, the first sacrificial gate structure and the second sacrificial gate structure.

9. The method of claim 8, further comprising:

planarizing the dielectric layer until a top surface of the first and second sacrificial gate structures are exposed and a portion of the dielectric layer remains overlying the polysilicon gate structure.

10. The method of claim 9, further comprising:

after planarizing the dielectric layer, removing the first sacrificial gate structure to form a first opening and the second sacrificial gate structure to form a second opening; and

forming a metal gate electrode in the first opening and in the second opening.

11. The method of claim 8, wherein the recess is greater than approximately 25 nm in depth.

12. The method of claim 8, further comprising:

forming a contact etch stop layer (CESL) on the polysilicon gate structure and the first sacrificial gate structure, wherein the CESL underlies the dielectric layer.

13. The method of claim 8, wherein the first and second active regions each have a top surface that is substantially co-planar with the first surface of the substrate.

14. A method, comprising:

providing a substrate having a polysilicon layer;

doping the polysilicon layer, wherein the doping includes a shallow implant of a first dopant type and a deep implant of a second dopant type, thereby forming a top portion of the polysilicon being a first dopant type-rich portion and an underlying portion of the polysilicon being a second dopant type-rich portion;

etching a recess in the polysilicon layer, after the doping, to provide a first portion having a first thickness and a second portion having a second thickness, the second thickness being less than the first thickness, wherein the etching the recess includes using the second dopant type-rich portion of the polysilicon layer as an etch stop;

after etching the polysilicon layer, patterning the polysilicon layer to form a first gate structure and a second gate structure, wherein the first gate structure is formed in the first portion of the polysilicon and the second gate structure is formed in the second portion of the polysilicon layer;

removing the first gate structure to form an opening;

forming a metal gate structure in the opening; and

forming contacts to each of the metal gate structure and the second gate structure.

15. The method of claim 14, wherein the

second dopant type is boron and creates a boron-rich underlying portion of the polysilicon layer.

16. The method of claim 14, wherein the second thickness is between approximately 25 nanometers and approximately 80 nanometers less than the first thickness.

17. The method of claim 14, further comprising:

forming an inter-layer dielectric (ILD) layer on the first and second gate structures, wherein the ILD layer has a third thickness above the first gate structure and a fourth thickness above the second gate structure, the fourth thickness being greater that the third thickness.

18. The method of claim 14, wherein the first dopant type is arsenic and creates an arsenic-rich top portion of the polysilicon layer.