Non-linear kerf monitor and design structure thereof

• US 9,070,651 B2
• Filed: 12/02/2011
• Issued: 06/30/2015
• Est. Priority Date: 12/02/2011
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Botula, Alan B., Joseph, Alvin J., Wolf, Randy L.
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US13/309,829
• Publication Number:
  US 20130141114A1
• Time in Patent Office: 1,306 Days
• Field of Search: 716/100, 716/118, 716/119, 716/136
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A non-linear kerf monitor, methods of manufacture and design structures are provided. The structure includes a coplanar waveguide provided in a kerf of a wafer between a first chip and a second chip. The structure further includes a shunt switch and a series switch coupled to the coplanar waveguide.

Claims

1. An integrated circuit having a structure comprising:

a coplanar waveguide provided in a kerf of a wafer between a first chip and a second chip; and

a shunt switch and a series switch coupled to the coplanar waveguide.

2. The integrated circuit of claim 1, wherein the shunt switch comprises:

an RF signal generator connected to a load resistor and a ground; and

a set of field effect transistors (FETs) in a stack connected to the RF signal generator, wherein;

a source of a first FET in the stack is connected to the RF signal generator;

drains of the FETs in the stack, except a last FET, are respectively connected to a source of a subsequent FET in the stack;

a drain of the last FET in the stack is connected to the ground;

gates of the FETs are individually connected to a respective resistor; and

the respective resistors are connected to a gate bias.

3. The integrated circuit of claim 2, wherein the set of FETs in the stack comprises six FETs.

4. The integrated circuit of claim 2, wherein the set of FETs in the stack have a gate width of about 4 μ

m, wherein the gate width generates harmonics and fits within spatial limitations of the kerf.

5. The integrated circuit of claim 2, wherein the set of FETs in the stack has a width of about 5 μ

m in order to fit within the kerf.

6. The integrated circuit of claim 1, wherein the series switch comprises:

an RF signal generator connected to a set of FETs in a stack and a ground GND; and

a load resistor connected to a last FET of the set of FETs in the stack, wherein;

the RF signal generator is connected to a source of a first FET of the set of FETs in the stack;

drains of the FETs in the stack, except a last FET, are respectively connected to a source of a subsequent FET in the stack;

a drain of a last FET of the set of FETs in the stack is connected to a load resistor;

gates of the FETs are individually connected to a respective resistor; and

the respective resistors are connected to a gate bias.

7. The integrated circuit of claim 6, wherein the set of FETs in the stack comprises six FETs.

8. The integrated circuit of claim 6, wherein the set of FETs in the stack have a gate width of about 1 μ

m, wherein the gate width increases coupling to a substrate and increases a sensitivity of harmonic tones.

9. The integrated circuit of claim 6, wherein the set of FETs in the stack has a width of about 5 μ

m in order to fit within the kerf.

10. The integrated circuit of claim 1, further comprising:

a first set of a plurality of pads for testing the shunt switch; and

a second set of a plurality of pads for testing the series switch.

11. The integrated circuit of claim 10, wherein the first set of the plurality of pads comprises:

a first pad for a gate bias;

a first set of ground pads separating the first pad and a second pad for an RF input;

a second set of ground pads separating the second pad and a third pad for an RF output; and

a third set of ground pads separating the third pad and a fourth pad for a body bias.

12. The integrated circuit of claim 10, wherein the second set of the plurality of pads comprises:

a first pad for a gate bias;

a first set of ground pads separating the first pad and a second pad for an RF input;

a second set of ground pads separating the second pad and a third pad for an RF output; and

a third set of ground pads separating the third pad and a fourth pad for a body bias.

13. A method comprising:

applying a gate bias to a shunt switch and a series switch, both coupled to a coplanar waveguide within a kerf space of a wafer;

injecting an RF power into one end of the shunt switch and one end of the series switch; and

measuring a fundamental power and a harmonic power at a load resistor of the shunt switch and a second load resistor of the series switch, while increasing the RF power.

14. The method of claim 13, wherein the fundamental power has a fundamental frequency and the harmonic power is measured at a second harmonic and a third harmonic.

15. The method of claim 13, wherein:

the shunt switch is measured in an off state; and

the series switch is measured in an on state.

16. The method of claim 13, wherein the fundamental and the harmonic power are measured using a 100 micron pitch probe or a 200 micron pitch probe.

17. A design structure tangibly embodied in a non-transitory machine readable storage medium for causing a machine to design, manufacture, or test an integrated circuit, the design structure comprising:

a coplanar waveguide provided in a kerf of a wafer between a first chip and a second chip; and

a shunt switch and a series switch coupled to the coplanar waveguide.

18. The design structure of claim 17, wherein the design structure comprises a netlist.

19. The design structure of claim 17, wherein the design structure resides on a storage medium as a data format for use in exchange of layout data of integrated circuits.

20. The design structure of claim 17, wherein the design structure resides in a programmable gate array.