Pads and pin-outs in three dimensional integrated circuits

• US 9,070,668 B2
• Filed: 01/06/2014
• Issued: 06/30/2015
• Est. Priority Date: 10/08/2002
• Status: Active Grant

• Current Assignee: Liberty Patents LLC
• Original Assignee: Yakimishu Co Ltd LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US14/147,881
• Publication Number:
  US 20140117413A1
• Time in Patent Office: 540 Days
• Field of Search: 257/209, 257/686, 257/E21.614, 257/E21.703, 257/E27.026, 326/41, 438/202
• US Class Current: 1/1
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.

Claims

1. A semiconductor device, comprising:

a first layer including a circuit;

a second layer including a plurality of circuits in a first plurality of locations;

a third layer including a plurality of pads in a second plurality of locations, wherein the plurality of pads are inaccessible from the first layer; and

a plurality of wire interconnects that are positioned through a first portion of the third layer and through a second portion of the second layer, wherein the circuit is configured to depend on the second layer to operate, wherein the first plurality of locations and the second plurality of locations are configured to be independent of the first layer, and wherein the first layer, the second layer, and the third layer form a stack.

2. The semiconductor device of claim 1, wherein the circuit is configured to provide field-programmable gate array (FPGA) functionality.

3. The semiconductor device of claim 2, wherein the circuit comprises a memory element for the FPGA functionality.

4. The semiconductor device of claim 1, wherein the first layer excludes pads.

5. The semiconductor device of claim 1, wherein the circuit is configured to provide application-specific integrated circuit (ASIC) functionality.

6. The semiconductor device of claim 5, wherein the circuit comprises a mask-programmable metal pattern for the ASIC functionality.

7. The semiconductor device of claim 1, wherein the plurality of circuits comprise a plurality of programmable logic circuits.

8. A method, comprising:

forming a stack comprising a first layer including a circuit, a second layer including a plurality of circuits in a first plurality of locations, a third layer including a plurality of pads in a second plurality of locations, and a plurality of wire interconnects that are positioned through a first portion of the third layer and through a second portion of the second layer, wherein the plurality of pads are inaccessible from the first layer; and

coupling a portion of the plurality of circuits to the plurality of pads, wherein the circuit is configured to depend on the second layer to operate, and wherein the first plurality of locations and the second plurality of locations are configured to be independent of the first layer.

9. The method of claim 8, wherein the circuit is configured to provide field-programmable gate array (FPGA) functionality.

10. The method of claim 9, wherein the circuit comprises a memory element for the FPGA functionality.

11. The method of claim 8, wherein the first layer excludes pads.

12. The method of claim 8, wherein the circuit is configured to provide application-specific integrated circuit (ASIC) functionality.

13. The method of claim 12, wherein the circuit comprises a mask-programmable metal pattern for the ASIC functionality.

14. The method of claim 8, wherein the plurality of circuits comprise a plurality of programmable logic circuits.

15. A semiconductor device, comprising:

a substrate including a plurality of circuits in a first plurality of locations;

a first layer including a circuit;

a second layer including a plurality of pads in a second plurality of locations, wherein the plurality of pads are inaccessible from the first layer; and

a plurality of wire interconnects that are positioned through a first portion of the second layer and through a second portion of the substrate, wherein the circuit is configured to depend on the substrate to operate, wherein the first plurality of locations and the second plurality of locations are configured to be independent of the first layer, and wherein the substrate, the first layer, and the second layer form a stack.

16. The semiconductor device of claim 15, wherein the circuit is configured to provide field-programmable gate array (FPGA) functionality.

17. The semiconductor device of claim 16, wherein the circuit comprises a memory element for the FPGA functionality.

18. The semiconductor device of claim 15, wherein the circuit is configured to provide application-specific integrated circuit (ASIC) functionality.

19. The semiconductor device of claim 18, wherein the circuit comprises a mask-programmable metal pattern for the ASIC functionality.

20. The semiconductor device of claim 15, wherein the plurality of circuits comprise a plurality of programmable logic circuits, and wherein the first layer excludes pads.