Semiconductor devices and methods of making the same

• US 9,070,721 B2
• Filed: 03/15/2013
• Issued: 06/30/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Arbuthnot, Roger M., St. Germain, Stephen
• Primary Examiner(s): Montalvo, Eva Y
• Assistant Examiner(s): LAIR, SAMUEL L
• Application Number:
  US13/834,612
• Publication Number:
  US 20140264806A1
• Time in Patent Office: 837 Days
• Field of Search: 257/727, 257/728, 257/666, 257/667, 257/668, 257/669, 257/670, 257/671, 257/672, 257/673, 257/674, 257/675, 257/676, 257/677, 257/E23.031, 257/E23.032, 257/E23.033, 257/E23.034, 257/E23.035, 257/E23.036, 257/E23.037, 257/E23.038, 257/E23.039, 257/E23.04, 257/E23.041, 257/E23.042, 257/E23.043, 257/E23.044, 257/E23.045, 257/E23.046, 257/E23.047, 257/E23.048, 257/E23.049, 257/E23.05, 257/E23.051, 257/E23.052, 257/E23.053, 257/E23.054, 257/E23.055, 257/E23.056, 257/E23.057, 257/E23.058, 257/E23.059
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04034 Bonding areas specifically adapted for strap connectors
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/32258 the layer connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/37011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/37012 Cross-sectional shape
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/40499 : Material of the auxiliary connecting means
• CPC Class Codes: H01L 2224/4103 : Connectors having different sizes
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73221 : Strap and wire connectors
• CPC Class Codes: H01L 2224/73263 : Layer and strap connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83815 : Reflow soldering
• CPC Class Codes: H01L 2224/84385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/84801 : Soldering or alloying
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/492 : Bases or plates or solder therefor
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49513 : having bonding material between chip and die pad
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/41 : of a plurality of strap connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/67 : of a plurality of connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In one embodiment, methods for making semiconductor devices are disclosed.

Claims

1. A semiconductor device comprising:

a first conductive substrate electrically coupled to a first lead, wherein the first conductive substrate comprises two or more elevated regions on a first side of the first conductive substrate, wherein each of the elevated regions comprises a planar surface on the first side of the first conductive substrate;

a semiconductor die comprising one or more first contact pads, a second contact pad, and a third contact pad, wherein the first contact pads are disposed on a first side of the semiconductor die, and wherein each of the first contact pads are soldered to at least one of the elevated regions such that each of the first contacts pads has two or more linear edges that are each laterally aligned and parallel with at least one edge of the planar surfaces on the elevated regions, and wherein at least one of the first contact pads is soldered to two or more of the elevated regions;

a second lead electrically coupled to the second contact pad of the semiconductor die; and

a third lead electrically coupled to the third contact pad of the semiconductor die.

2. The semiconductor device of claim 1, wherein the first conductive substrate comprises at least 10 elevated regions.

3. The semiconductor device of claim 2, wherein a number of the elevated regions on the first side of the first conductive substrate is greater than a number of the elevated regions soldered to the first contact pads of the semiconductor die.

4. The semiconductor device of claim 1, further comprising a second conductive substrate soldered to the second contact pad, and wherein the second conductive substrate is electrically coupled to the second lead.

5. The semiconductor device of claim 1, wherein a number of the elevated regions on the first side of the first conductive substrate is greater than a number of the contact pads soldered to the first conductive substrate.

6. The semiconductor device of claim 1, wherein no more than about 95% of a total surface area of the first contact pads is soldered to the elevated regions.

7. The semiconductor device of claim 1, wherein at least a portion of the elevated regions on the first side of the conductive substrate have different sizes.

8. The semiconductor device of claim 1, wherein the elevated regions are evenly spaced along a first direction.

9. The semiconductor device of claim 1, wherein the elevated regions on the first side of the first conductive substrate are arranged in an array having multiple rows and multiple columns, each of the rows having the same number of elevated regions and each of the columns having the same number of elevated regions.

10. The semiconductor device of claim 1, wherein at least one of the first contact pads is soldered to three or more of the elevated regions.

12. The semiconductor device of claim 1, wherein at least one of the elevated regions on the first conductive substrate is not soldered to the semiconductor die.

13. The semiconductor device of claim 1, wherein at least one of the elevated regions on the first conductive substrate has only a portion of the planar surface soldered to the first contact pads.

14. The semiconductor device of claim 1, wherein the elevated regions on the first conductive substrate have different dimensions.

15. The semiconductor device of claim 1, wherein the planar surfaces on the elevated regions have a polygonal shape.

11. A semiconductor device comprising:

a lead frame comprising a first contact electrically coupled to a first lead of the semiconductor device;

a conductive clip electrically coupled to a second lead on the semiconductor device, wherein the conductive clip comprises two or more elevated regions on a first side of the conductive clip, wherein each of the elevated regions comprises a planar surface on the first side of the conductive clip; and

a semiconductor die comprising;

a first contact pad on a first side of the semiconductor die, wherein the first contact pad is soldered to the first contact on the lead frame;

one or more second contact pads on a second a side of the semiconductor die, wherein each of the second contact pads are soldered to at least one of the elevated regions on the first side of the conductive clip such that each of the second contacts pads has two or more linear edges that are each laterally aligned and parallel with at least one edge of the planar surfaces on the elevated regions, and wherein at least one of the second contact pads is soldered to two or more of the elevated regions; and

a third contact pad on the semiconductor die, wherein the third contact pad is electrically coupled to a third lead of the semiconductor device.

16. The semiconductor device of claim 11, wherein at least one of the second contact pads is soldered to three or more of the elevated regions.

17. The semiconductor device of claim 11, wherein the first contact of the lead frame comprises one or more second elevated regions on a first side of the first contacts of the lead frame, wherein each of the second elevated regions comprises a planar surface on the first side of the first contact of the lead frame, and wherein the first contact pad of the semiconductor die is soldered to the second elevated regions on the first contact of the lead frame such that the first contact pad of the semiconductor die has two or more linear edges that each laterally aligned and parallel with at least one edge of the planar surfaces on the second elevated regions on the first contact of the lead frame.