Bulk finFET with controlled fin height and high-k liner

• US 9,070,771 B2
• Filed: 08/15/2014
• Issued: 06/30/2015
• Est. Priority Date: 09/06/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Reznicek, Alexander, Adam, Thomas N., Cheng, Kangguo, Khakifirooz, Ali
• Primary Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US14/460,921
• Publication Number:
  US 20140353721A1
• Time in Patent Office: 319 Days
• Field of Search: 257/192
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate. A semiconductor material is formed in the openings through the material stack. The first dielectric layer is removed selectively to the second dielectric layer and the semiconductor material. A gate structure is formed on a channel portion of the semiconductor material. In some embodiments, the method may provide a plurality of finFET or trigate semiconductor device in which the fin structures of those devices have substantially the same height.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first semiconductor material;

a plurality of punch through doped semiconductor structures in contact with the semiconductor substrate, in which adjacent punch through doped semiconductor structures are separated from one another by a dielectric isolation material, wherein the dielectric isolation material comprises a high-k dielectric layer having an upper surface that is substantially coplanar with an upper surface of the plurality of the punch through doped semiconductor structures;

a plurality of fin structures of a second semiconductor material, wherein each fin structure of the plurality of fin structures is present on a punch through doped semiconductor structure of the plurality of punch through doped semiconductor structures, wherein said each fin structure of the plurality of fin structures has a substantially same height as measured from the surface of the semiconductor substrate; and

a gate structure present on a channel portion of said each fin structure of the plurality of fin structures.

2. The semiconductor device of claim 1, wherein the first semiconductor material of the semiconductor substrate is different from the second semiconductor material of the plurality of fin structures.

3. The semiconductor device of claim 1, wherein the first semiconductor material is selected from the group consisting of silicon, germanium silicon germanium, silicon doped with carbon (Si:

C), III-V semiconductors and a combination thereof, and the second semiconductor material is selected from the group consisting of silicon, germanium silicon germanium, silicon doped with carbon (Si;

C), III-V semiconductors and a combination thereof.

4. The semiconductor device of claim 1, wherein the plurality of punch through doped semiconductor structures is comprised of a same semiconductor material as the second semiconductor material of the plurality of fin structures.

5. The semiconductor device of claim 1, wherein the high-k dielectric layer is a hafnium containing material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, and hafnium silicon oxynitride and combinations thereof.

6. The semiconductor device of claim 1, wherein each punch through doped semiconductor structure of the plurality of punch through doped semiconductor structures is doped with carbon or is doped to have an opposite conductivity type than source and drain regions that are present on opposing sides of the channel portion for each fin structure of the plurality of fin structures.

7. The semiconductor device of claim 1, wherein said each fin structure of the plurality of fin structures having the substantially same height comprises a differential in height of +/−

10 nm or less.

8. The semiconductor device of claim 1, wherein said each fin structure of the plurality of fin structures having the substantially same height comprises a differential in height of +/−

5 nm or less.

9. The semiconductor device of claim 1, wherein the gate structure comprises a gate dielectric on sidewall and upper surfaces of said each fin structure, and a gate conductor on the gate dielectric.

10. The semiconductor device of claim 8, wherein the semiconductor device is a tri-gate semiconductor device.

11. The semiconductor device of claim 1, further comprising a dielectric cap on an upper surface of said each fin structure of the plurality of the fin structures.

12. The semiconductor device of claim 10, wherein the gate structure on the channel portion of the semiconductor material comprises a gate dielectric on sidewall of said each fin structure and on the dielectric cap, and a gate conductor on the gate dielectric.

13. A semiconductor device comprising:

a semiconductor substrate of a first semiconductor material;

a plurality of punch through doped semiconductor structures in contact with the semiconductor substrate, in which adjacent punch through doped semiconductor structures are separated from one another by a dielectric isolation material, wherein the dielectric isolation material comprises a layered structure of an oxide layer that is in contact with the semiconductor substrate and a high-k dielectric layer that is present on the oxide layer;

a plurality of fin structures of a second semiconductor material, wherein each fin structure of the plurality of fin structures is present on a punch through doped semiconductor structure of the plurality of punch through doped semiconductor structures, wherein said each fin structure of the plurality of fin structures has a substantially same height as measured from the surface of the semiconductor substrate; and

a gate structure present on a channel portion of said each fin structure of the plurality of fin structures.

14. A semiconductor device comprising:

a semiconductor substrate of a first semiconductor material;

a plurality of punch through doped semiconductor structures in contact with the semiconductor substrate, in which adjacent punch through doped semiconductor structures are separated from one another by a dielectric isolation material;

a plurality of fin structures of a second semiconductor material, wherein each fin structure of the plurality of fin structures is present on a punch through doped semiconductor structure of the plurality of punch through doped semiconductor structures, wherein said each fin structure of the plurality of fin structures has a substantially same height as measured from the surface of the semiconductor substrate, and wherein each of the punch through doped semiconductor structure of the plurality of punch through doped semiconductor structures is doped with carbon or is doped to have an opposite conductivity type than source and drain regions that are present on opposing sides of the channel portion for each fin structure of the plurality of fin structures; and

a gate structure present on a channel portion of said each fin structure of the plurality of fin structures.