Semiconductor device packages having electromagnetic interference shielding and related methods

• US 9,070,793 B2
• Filed: 05/24/2011
• Issued: 06/30/2015
• Est. Priority Date: 08/02/2010
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Liao, Kuo-Hsien, Chen, Jian-Cheng, Chan, Chi-Hong, Ueng, Chian-Her, Sun, Yu-Hsiang
• Primary Examiner(s): Moore, Whitney T
• Assistant Examiner(s): GALVIN III, JOSEPH M
• Application Number:
  US13/114,915
• Publication Number:
  US 20120025356A1
• Time in Patent Office: 1,498 Days
• Field of Search: 257/659, 257/664, 257/662, 257/508, 257/660
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/0103 Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

The semiconductor device package includes a conformal shield layer applied to the exterior surface of the encapsulant, and an internal fence or separation structure embedded in the encapsulant. The fence separates the package into various compartments, with each compartment containing at least one die. The fence thus suppresses EMI between adjacent packages. The package further includes a ground path connected to the internal fence and conformal shield.

Claims

1. A semiconductor device package, comprising:

a substrate including a carrier surface;

a plurality of dies coupled to the carrier surface of the substrate and electrically connected to the substrate;

an electromagnetic interference (EMI) shield, including a connecting element and a shield layer that are discrete components, the connecting element including a first end and a second end opposite the first end, wherein the first end has a larger, lateral surface area than the second end;

a first grounding segment coupled to the carrier surface, wherein the second end of the connecting element is coupled to the first grounding segment;

at least one second grounding segment disposed at a periphery of the substrate wherein the shield layer is coupled to the at least one second grounding segment; and

a package body covering the dies and partially covering the first end of the connecting element, a portion of the first end of the connecting element spaced from the substrate being exposed from the package body;

wherein the connecting element extends between adjacent ones of the dies, thereby dividing the semiconductor device package into a plurality of compartments, with each compartment containing at least one of the dies; and

wherein the shield layer is disposed over the package body and the exposed portion of the first end of the connecting element.

2. The semiconductor device package of claim 1, further comprising a plurality of second grounding segments, and wherein the second grounding segments circumscribe the periphery of substrate and provide additional EMI shielding to the semiconductor device package.

3. The semiconductor device package of claim 2, wherein the shield layer is coupled to lateral surfaces of the second grounding segments.

4. The semiconductor device package of claim 1, wherein the shield layer is coupled to the first grounding segment through the connecting element.

5. The semiconductor device package of claim 1, wherein the package body has an opening corresponding to the exposed portion of the connecting element, and the shield layer has a depression overlying the opening.

6. The semiconductor device package of claim 1, wherein the connecting element includes an angular portion in a region of the exposed portion.

7. A semiconductor device package, comprising:

a substrate including a carrier surface;

a plurality of dies coupled to the carrier surface of the substrate and electrically connected to the substrate, wherein each of the plurality of dies has an active surface;

an electromagnetic interference (EMI) shield, including a connecting element extending vertically from the carrier surface and a shield layer, the connecting element and the shield layer being discrete components;

a first grounding segment coupled to the carrier surface, and a plurality of second grounding segments coupled to a periphery of the substrate, wherein the first grounding segment is coupled to a first end of the connecting element; and

an encapsulant covering the dies and partially covering the connecting element including at least two oppositely facing surfaces of the connecting element, an exposed portion of the connecting element being opposite the first end of the connecting element and uncovered by the encapsulant;

wherein the connecting element includes an angular portion in a region of the exposed portion such that the angular portion comprises a larger lateral surface area than a lateral surface area of the first end of the connecting element; and

wherein the shield layer is disposed over the package body and connected to the exposed angular portion of the connecting element.

8. The semiconductor device package of claim 7, wherein the active surface of at least one of the dies faces the substrate and wherein the connecting element includes a plurality of openings that promote the encapsulant to underfill the die.

9. The semiconductor device package of claim 7, wherein at least one of the dies is electrically connected to the substrate by at least one wirebond and wherein the connecting element includes a plurality of openings that promote the encapsulant covering the at least one wirebond.

10. The semiconductor device package of claim 9, wherein the openings extend along a length of the connecting element at an edge that is adjacent the substrate.

11. The semiconductor device package of claim 10, wherein a subset of the openings are diamond shaped and arranged in a grid pattern.

12. The semiconductor device package of claim 7, wherein the shield layer has a depression overlying the exposed angular portion of the connecting element.

13. The semiconductor device package of claim 7, wherein the connecting element is electrically connected to the first grounding segment and the shield layer is electrically connected to at least one of the plurality of the second grounding segments.

14. A semiconductor device package, comprising:

a substrate including a carrier surface;

a plurality of dies coupled to the carrier surface of the substrate and electrically connected to the substrate, wherein each of the plurality of dies has an active surface;

an electromagnetic interference (EMI) shield, including a connecting element extending vertically from the carrier surface and a shield layer, the connecting element and the shield layer being discrete components;

a plurality of first grounding segments coupled to a periphery of the substrate; and

an encapsulant covering the dies and partially covering the connecting element including at least two oppositely facing surfaces of the connecting element, an exposed portion of the connecting element being opposite a first end of the connecting element and uncovered by the encapsulant;

wherein the connecting element includes an angular portion in a region of the exposed portion such that the angular portion comprises a larger, lateral surface area than a lateral surface area of the first end of the connecting element; and

wherein the shield layer is disposed over the package body and connected to the exposed angular portion of the connecting element so that the connecting element is coupled to the first grounding segment through the shield layer.

15. The semiconductor device package of claim 14 wherein the active surface of at least one of the dies faces the substrate and wherein the connecting element includes a plurality of openings that promote the encapsulant to underfill the die.

16. The semiconductor device package of claim 14, wherein at least one of the dies is electrically connected to the substrate by at least one wirebond and wherein the connecting element includes a plurality of openings that promote the encapsulant covering the at least one wirebond.

17. The semiconductor device package of claim 16, wherein a subset of the openings are diamond shaped and arranged in a grid pattern.

18. The semiconductor device package of claim 14, wherein the shield layer has a depression overlying the exposed angular portion of the connecting element.

19. The semiconductor device package of claim 14 wherein the connecting element is electrically connected to a second grounding segment coupled to the substrate.

20. The semiconductor device package of claim 19 wherein the shield layer is coupled to the second grounding segment through the connecting element.