Photonic device

• US 9,070,815 B2
• Filed: 06/21/2013
• Issued: 06/30/2015
• Est. Priority Date: 08/23/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Kwang-hyun, Shin, Dong-jae, Ji, Ho-chul
• Primary Examiner(s): PINKNEY, DAWAYNE
• Application Number:
  US13/924,487
• Publication Number:
  US 20140055838A1
• Time in Patent Office: 739 Days
• Field of Search: 359278-279, 359/315, 359/245, 359/247, 359251-252, 359/254, 359/108, 359237-238, 359290-292, 359/298, 359300-302, 385 1- 3, 385/40, 385129-132, 385/5, 385 8- 9
• US Class Current: 1/1
• CPC Class Codes: G02F 1/015 based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction G02F1/03 takes precedence
• CPC Class Codes: G02F 1/025 in an optical waveguide structure G02F1/017, G02F1/2257 take precedence
• CPC Class Codes: G02F 1/2257 the optical waveguides being made of semiconducting material
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type

Abstract

A photonic device is provided. The photonic device includes: a semiconductor layer including first and second regions; an insulating layer covering the semiconductor layer; and first and second plugs extending to pass through the insulating layer and electrically connected to the corresponding first and second regions. The first plug is in a rectifying contact with the first region, and the second plug is in an ohmic contact with the second region.

Claims

1. A photonic device comprising:

a semiconductor layer including a first region, a second region, and a third region disposed between the first and second regions;

an insulating layer covering the semiconductor layer; and

first and second plugs extending to pass through the insulating layer and electrically connected to the corresponding first and second regions;

wherein;

the third region is configured to allow charge carriers to flow between the first and second regions;

the third region includes a portion that protrudes from a surface of the first or second region;

the first plug is in a rectifying contact with the first region; and

the second plug is in an ohmic contact with the second region.

2. The photonic device of claim 1, further comprising:

first and second electrode pads disposed on the insulating layer;

wherein the first and second regions are electrically connected with the first and second electrode pads by the respective first and second plugs.

3. The photonic device of claim 1, wherein:

the first and second regions have substantially similar charge carrier concentrations.

4. The photonic device of claim 3, wherein the first and third regions are intrinsic regions.

5. The photonic device of claim 3, wherein the first and third regions are extrinsic regions doped with dopants of a first or second conductivity type.

6. The photonic device of claim 1, wherein:

the second region is doped with a dopant of a first or second conductivity type; and

the second region has a higher charge carrier concentration than the first region.

7. The photonic device of claim 1, wherein:

the second region includes a first doped region of a first or second conductivity type and a second doped region of the first or second conductivity type;

the second doped region has a higher charge carrier concentration than the first doped region; and

the second plug is in an ohmic contact with the second doped region.

8. The photonic device of claim 1, wherein at least one of the first plug and the second plug has a bottom surface contacting a top surface of the corresponding first region or second region.

9. The photonic device of claim 1, wherein at least one of the first plug and the second plug has a bottom surface buried in the corresponding first region or second region.

10. The photonic device of claim 1, further comprising:

a third plug extending to pass through the insulating layer and electrically connected to the first region;

wherein the third plug is in a rectifying contact with the first region.

11. The photonic device of claim 1, wherein the first plug has a different width from the second plug.

12. The photonic device of claim 1, wherein:

the semiconductor layer further comprises a third region that is disposed between the first and second regions, allows charges carriers to flow between the first and second regions, and provides a path along which an optical signal moves; and

the first through third regions form a phase shifter.

13. The photonic device of claim 1, wherein the semiconductor layer further comprises a third region that protrudes from one side with respect to the first and second regions and is separated from the first and second plugs.

14. The photonic device of claim 1, wherein:

the semiconductor layer further comprises a third region that is disposed between the first and second regions and is configured to generate charge carriers in response to an optical signal; and

the first through third regions form a photodiode.

15. The photonic device of claim 1, wherein:

the semiconductor layer further comprises a first layer having the first region disposed at a top portion thereof and a third region configured to generate charge carriers in response to an optical signal, and a second layer disposed below the first layer and having the second region at a top portion thereof; and

the first through third regions form a photodiode.

16. The photonic device of claim 1, wherein:

the first plug is configured to transmit a first electrical signal to the semiconductor layer; and

the second plug is configured to transmit a second electrical signal to the semiconductor layer.

17. A system, comprising:

at least one electro-optical modulator configured to modulate an optical signal to generate a modulated optical signal;

wherein each electro-optical modulator includes a phase shifter comprising;

a semiconductor layer including a first region, a second region, and a third region disposed between the first and second regions;

an insulating layer covering the semiconductor layer; and

first and second plugs extending to pass through the insulating layer and electrically connected to the corresponding first and second regions;

wherein;

the third region is configured to allow charge carriers to flow between the first and second regions;

the third region includes a portion that protrudes from a surface of the first or second region;

the first plug is in a rectifying contact with the first region and

the second plug is in an ohmic contact with the second region.

18. A method, comprising:

forming a semiconductor layer including first and second regions on a substrate;

doping the second region;

forming an insulating layer over the semiconductor layer;

forming a rectifying contact with the first region that passes through the insulating layer; and

forming an ohmic contact with the second region that passes through the insulating layer.

19. The method of claim 18, wherein:

forming the semiconductor layer comprises forming the semiconductor layer with a third region protruding from the first and second regions;

forming a pattern over the first and third regions that exposes at least part of the second region; and

doping the second region after forming the pattern.

20. The method of claim 18, wherein doping the second region comprises doping the second region with a carrier concentration higher than a carrier concentration of the first region.