Light emitting device package and manufacturing method thereof

• US 9,070,852 B2
• Filed: 11/14/2011
• Issued: 06/30/2015
• Est. Priority Date: 12/02/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sang Hyun, Hwang, Seong Deok
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Kim, Sun M
• Application Number:
  US13/295,850
• Publication Number:
  US 20120138988A1
• Time in Patent Office: 1,324 Days
• Field of Search: 438/667, 257/E33.057
• US Class Current: 1/1
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/48 characterised by the semiconductor body packages
• CPC Class Codes: H01L 33/483 Containers
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/50 Wavelength conversion elements
• CPC Class Codes: H01L 33/502 Wavelength conversion materials
• CPC Class Codes: H01L 33/507 the elements being in intimate contact with parts other than the semiconductor body or integrated with parts other than the semiconductor body
• CPC Class Codes: H01L 33/56 Materials, e.g. epoxy or silicone resin
• CPC Class Codes: H01L 33/58 Optical field-shaping elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A light emitting device (LED) package and a manufacturing method thereof are provided. The LED package includes an LED including a first electrode pad and a second electrode pad disposed on one surface thereof; a bonding insulating pattern layer configured to expose the first electrode pad and the second electrode pad; a substrate including a via hole bored from a first surface to a second surface and a wiring metal layer formed on an inner surface of the via hole to extend to a part of the second surface; and a bonding metal pattern layer bonded to the wiring metal layer exposed through the via hole at the first surface of the substrate and also bonded to the first electrode pad and the second electrode pad.

Claims

1. A method for manufacturing a light emitting device (LED) package, comprising steps of:

preparing a first substrate that comprises a sapphire substrate, an LED on the sapphire substrate formed with a first electrode pad and a second electrode pad disposed on one surface of the LED, and a bonding insulating pattern layer exposing the first electrode pad and the second electrode pad;

preparing a second substrate that comprises a plurality of via holes bored from a first surface to a second surface, and a wiring metal layer formed on inner surfaces of the plurality of via holes, extending to a part of the second surface;

forming a bonding metal pattern layer to be bonded to the wiring metal layer exposed through the plurality of via holes at the first surface of the second substrate;

mounting the first substrate to the second substrate such that the first electrode pad and the second electrode pad face the bonding metal pattern layer;

bonding the first substrate and the second substrate by melting the bonding insulating pattern layer at a predetermined temperature and pressing the first substrate from an upper part;

forming an uneven surface pattern on the first substrate by removing the sapphire substrate and etching an exposed surface of the first substrate;

forming an insulating layer and a phosphor resin layer sequentially on the uneven surface pattern of the first substrate; and

manufacturing the LED package separated into unit chips by processing the first substrate and the second substrate, so that a size of the bonding insulating pattern layer is substantially the same as a size of the second substrate,

wherein the step of preparing the first substrate comprises;

forming a light emission structure comprising a first nitride-based semiconductor layer, an active layer, and a second nitride-based semiconductor layer, on the sapphire substrate;

etching the active layer and the second nitride-based semiconductor layer so that a part of the first nitride-based semiconductor layer is exposed;

forming the first electrode pad on the first nitride-based semiconductor layer and forming the second electrode pad on the second nitride-based semiconductor layer;

after processing by oxygen plasma one surface of the light emission structure where the first electrode pad and the second electrode pad are formed, coating a bonding insulating material to cover the first electrode pad and the second electrode pad on one surface where the first electrode pad and the second electrode pad are formed; and

forming the bonding insulating pattern layer by patterning the bonding insulating material so that the first electrode pad and the second electrode pad are exposed.

2. The method of claim 1, wherein the manufacturing of the LED package separated into unit chips, comprises:

applying a transparent resin on the phosphor resin; and

cutting the first substrate and the second substrate into separate unit chips.

3. The method of claim 1, wherein the preparing of the second substrate comprises:

forming the plurality of via holes by etching a conductive substrate;

forming an insulating layer on a surface of the conductive substrate formed with the plurality of via holes;

forming a metal seed layer on the insulation layer, the metal seed layer extending from an inner surface of each of the plurality of via holes to the second surface; and

forming the wiring metal layer by plating the metal seed layer with a metal material extending from an inner surface of each of the plurality of via holes to a part of the second surface.

4. The method of claim 1, wherein the plurality of via holes each have a diameter increasing from the first surface toward the second surface such that the inner surface has an inclination angle of about 65°

to about 90°

.

5. The method of claim 3, wherein the forming of the wiring metal layer plates the metal seed layer with a uniform thickness of the metal material into the same shape as an inside of each of the plurality of via holes.

6. The method of claim 1, wherein the forming of the bonding metal pattern layer is performed such that the bonding metal pattern layer is meshed with the first electrode pad and the second electrode pad exposed through the bonding insulating pattern layer at the first substrate and such that an outer surface of the bonding metal pattern layer is separated from the bonding insulating pattern layer.