Memory controller for heterogeneous configurable integrated circuits

• US 9,071,246 B2
• Filed: 09/14/2007
• Issued: 06/30/2015
• Est. Priority Date: 09/14/2007
• Status: Expired due to Fees

• Current Assignee: Agate Logic, Inc.
• Original Assignee: Agate Logic, Inc.
• Inventors: Subramaniam, Suresh, Krishnappa, Mukunda, Chu, Pohrong R., Golbus, Jason, How, Dana L.
• Primary Examiner(s): Nguyen, Vanthu
• Assistant Examiner(s): ALROBAIE, KHAMDAN N
• Application Number:
  US11/855,740
• Publication Number:
  US 20090072856A1
• Time in Patent Office: 2,846 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

Claims

1. A system comprising:

a configurable memory controller including a plurality of configuration bits configured to indicate at least one of memory type, address, data width, and operating frequency;

wherein the configurable memory controller comprise a configuration registers to store the plurality of the configuration bits and a mode register bits;

a dedicated interface coupled to the configuration registers by a mode register data bus, wherein the dedicated interface is used by the user for setting the values in the configuration registers;

a memory interface; and

a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array wherein each of the plurality of interconnect stations includes a first set of connectors and a second set of connectors wherein the first set of connectors is configured to couple to an adjacent interconnect station via a plurality of pipelined buses,

wherein the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations,

wherein the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations,

wherein the second set of connectors is configured to connect to a programmable logic block (“

PLB”

).

2. The system of claim 1, wherein the memory interface comprises a configurable general purpose input/output (GPIO) block operably coupled to the configurable memory controller using the first and the second interconnect stations of the plurality of interconnect stations.

3. The system of claim 2, wherein the configurable memory controller and the configurable GPIO block are operable to cooperatively execute a first data transaction with a memory device connected to the memory interface.

4. The system of claim 3, wherein the configurable memory controller comprises an address first-in first-out (FIFO) device and is operable to perform an address function and a control function associated with the first data transaction.

5. The system of claim 4, wherein the configurable memory controller is operable in at least one mode selected from a group consisting of:

BYPASS, PRECHARGE, AUTO_REFRESH, POWER_DOWN, REFRESH, NOP, ACTIVATE, READ, WRITE, DESELECT, and LD_MODE.

6. The system of claim 3, wherein the configurable GPIO block comprises a read data FIFO device and a write data FIFO device and is operable to perform a data path function associate with the first data transaction.

7. The system of claim 2, wherein the configurable integrated circuit is disposed on a monolithic semiconductor substrate, wherein the memory device is external to the monolithic semiconductor substrate, and wherein the configurable GPIO block borders the monolithic semiconductor substrate.

8. The configurable integrated circuit of claim 7, wherein the configurable memory controller sends a command to power down at least a portion of the memory device subsequent to a counter counting to a predetermined count and there is no pending access to the portion of the memory device.

9. The system of claim 1, wherein the configurable memory controller comprises a datapath that is decoupled from at least one selected from a group consisting of an address path and a control path.

10. The system of claim 1, wherein the configurable memory controller supports double data rate (DDR), reduced latency dynamic random access memory (RL DRAM), and quad data rate synchronous dynamic random access memory (QDR SDRAM).

11. A programmable logic system comprising:

a configurable memory controller having a configuration register capable of providing memory configuration;

wherein the configuration register includes a plurality of mode register bits, and a plurality of configuration bits, wherein the plurality of configuration bits are programmable to indicate memory type, memory address, data width, and operating frequency;

a dedicated interface coupled to the configuration registers by a mode register data bus, wherein the dedicated interface is used by the user for setting the values in the configuration registers;

a memory interface coupled to the configurable memory controller and configured to include a configurable general purpose input/output (GPIO) block coupled to the configurable memory controller using the first and the second interconnect stations of the plurality of interconnect stations; and

a configurable high speed communications fabric coupled to the configurable memory controller and including a plurality of interconnect stations arranged in an array wherein each of the plurality of interconnect stations includes a set of ports and a set of ramps wherein the set of ramps is configured to couple to an adjacent interconnect station via a plurality of pipelined buses, wherein the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit.

12. The system of claim 11, wherein the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations.

13. The system of claim 11, wherein the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface.

14. The system of claim 11, wherein the configurable memory controller and the configurable GPIO block are operable to cooperatively execute a first data transaction with a memory device connected to the memory interface.

15. The system of claim 14, wherein the configurable memory controller comprises an address first-in first-out (FIFO) device and is operable to perform an address function and a control function associated with the first data transaction.

16. The system of claim 11, wherein the configurable GPIO block comprises a read data FIFO device and a write data FIFO device and is operable to perform a data path function associate with the first data transaction.

17. The system of claim 11, wherein the configurable memory controller comprises a data path that is decoupled from at least one selected from a group consisting of an address path and a control path.

18. The system of claim 11, wherein the configurable memory controller is operable in a mode selected from one of BYPASS mode, PRECHARGE mode, AUTO_REFRESH mode, POWER_DOWN mode, REFRESH mode, NOP mode, ACTIVATE, READ mode, WRITE, DESELECT mode, and LD_MODE mode.

19. The system of claim 11, wherein the configurable memory controller supports double data rate (DDR), reduced latency dynamic random access memory (RL DRAM), and quad data rate synchronous dynamic random access memory (QDR SDRAM).