Compensation for digitally controlled oscillator apparatus and method

• US 9,071,253 B2
• Filed: 11/09/2011
• Issued: 06/30/2015
• Est. Priority Date: 11/09/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Li, Shenggao
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US13/997,589
• Publication Number:
  US 20130278347A1
• Time in Patent Office: 1,329 Days
• Field of Search: 331/16, 331/1.A, 331/34, 331/167, 331/177.V, 331/117.R, 331/117.FE
• US Class Current: 1/1
• CPC Class Codes: H03B 1/00 Details
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Abstract

Automatic digital sensing and compensation of frequency drift caused by temperature, aging, and/or other effects may be provided by including a compensation capacitor array and a sensing logic. The sensing logic may be configured to detect a drift in a first control signal and to provide the compensation capacitor array with a second control signal. The second control signal is configured to cause an adjustment of capacitance in the compensation capacitor array based on the detected drift in the first control signal.

Claims

1. An apparatus, comprising:

a first capacitor array;

a sensing logic coupled to the first capacitor array and configured to detect a drift in a first control signal and to provide the first capacitor array with a second control signal, wherein the second control signal is configured to cause an adjustment of capacitance in the first capacitor array based on the detected drift in the first control signal; and

a second capacitor array to receive the first control signal and to provide fine frequency tuning in a phase-locked loop.

2. The apparatus of claim 1, wherein the first capacitor array is configured to compensate for temperature or aging in a phase-locked loop.

3. The apparatus of claim 1, further comprising:

a third capacitor array coupled to receive a third control signal to enable or disable capacitors in the third capacitor array to provide coarse frequency tuning.

4. The apparatus of claim 1, wherein the second control signal is configured to cause the adjustment of capacitance in the first capacitor array by enabling or disabling capacitors in the first capacitor array.

5. The apparatus of claim 1, wherein the sensing logic is configured to detect the drift in the first control signal based at least in part on a deviation from a threshold.

6. The apparatus of claim 1, further comprising:

a digital loop filter logic coupled to provide a phase difference to the sensing logic.

7. The apparatus of claim 1, wherein the sensing logic is included in a digital loop filter.

8. The apparatus of claim 1, wherein the first capacitor array includes a plurality of fine-tuning capacitor arrays identical to a second capacitor array coupled to the sensing logic.

9. A method, comprising:

detecting by a detection circuit, a drift in a first control word;

based at least in part on the detected drift, adjusting by the detection circuit, a second control word to be provided to a first capacitor array to cause an adjustment in capacitance based on the detected drift in the first control word; and

providing the first control word to a second capacitor array to cause fine frequency tuning in the second capacitor array.

10. The method of claim 9, wherein the adjustment in capacitance is configured to re-center a frequency of a digitally controlled oscillator that includes the first capacitor array.

11. The method of claim 9, further comprising:

receiving, by the detection circuit, a digital output signal from a digital loop filter logic.

12. The method of claim 9, wherein the detecting and adjusting occur in an all-digital phase locked loop.

13. The method of claim 9, wherein the detecting the drift in the first control word includes detecting a frequency deviation from a center of a fine-tuning curve.

14. The method of claim 9, wherein the detecting the drift in the first control word includes comparing the first control word to a threshold control value.

15. A system, comprising:

a processor;

a communication interface coupled to the processor, the communication interface including;

a first capacitor array;

a second capacitor array; and

a sensing logic coupled to the first capacitor array and the second capacitor array; and

a memory including a non-transitory computer readable medium having instructions executable by the processor to cause the communication interface to;

detect by the sensing logic a drift in a first control word; and

based at least in part on the detected drift, adjust, a second control word to be provided to the first capacitor array to cause an adjustment in capacitance based on the detected drift in the first control word.

16. The system of claim 15, wherein the first capacitor array, the second capacitor array, and the sensing logic are included in a digitally controlled oscillator.

17. The system of claim 16, further comprising:

a third capacitor array in the digitally controlled oscillator to provide coarse frequency tuning.

18. The system of claim 17, wherein the third capacitor array is configured to provide the coarse frequency tuning by cancelling process-voltage-temperature variation.

19. The system of claim 15, further comprising:

a digital loop filter logic coupled to provide a signal including a phase difference to the sensing logic.

20. The system of claim 15, wherein the first capacitor array, the second capacitor array, and the sensing logic are included in an all-digital phase-locked loop.