Semiconductor device

• US 9,071,415 B2
• Filed: 06/04/2013
• Issued: 06/30/2015
• Est. Priority Date: 06/08/2012
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Takeuchi, Masahiro
• Primary Examiner(s): Ha, Dac
• Assistant Examiner(s): Tieu, Janice
• Application Number:
  US13/909,598
• Publication Number:
  US 20130329843A1
• Time in Patent Office: 756 Days
• Field of Search: 375373-376, 375/344, 375/327
• US Class Current: 1/1
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H04B 1/69 Spread spectrum techniques
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A frequency tracking loop receives a result from a phase detector that detects an advance and a retard of a phase between input data and an extracted clock signal, and conducts a control to reduce a frequency deviation between the input data and the extracted clock signal. A phase interpolator adjusts a phase of the clock signal subjected to spread-spectrum frequency modulation on the basis result of the frequency deviation in the frequency tracking loop, and outputs the extracted clock signal. In the frequency tracking loop, the frequency deviation between the data signal and the clock signal is corrected to offset a variation of the frequency of the clock signal, on the basis of the frequency modulation information related to the clock signal subjected to the spread-spectrum frequency modulation which is input to the phase interpolator. The frequency of the clock signal seemingly follows the frequency of the data signal.

Claims

1. A semiconductor device having a clock recovery circuit, comprising:

a phase detector that detects an advance and a retard of a phase between input data and an extracted clock signal;

a frequency tracking loop that conducts a tracking control to reduce a frequency deviation between a frequency of the input data and a frequency of the extracted clock signal on the basis of a result of integrating a detection result of the phase detector together; and

a phase interpolator that receives a clock signal subjected to spread-spectrum frequency modulation from a clock generator, adjusts a phase of the clock signal on the basis of a detection result of the frequency deviation in the frequency tracking loop, and supplies the clock signal to the phase detector as the extracted clock signal,

wherein the frequency tracking loop receives frequency modulation information corresponding to the clock signal subjected to the spread-spectrum frequency modulation from the clock generator, corrects the frequency deviation on the basis of the frequency modulation information, and offsets the frequency modulation of the clock signal.

2. The semiconductor device according to claim 1,

wherein the frequency tracking loop includes a circuit that adds or subtracts the frequency modulation information to or from an output or an input of a first integrator that integrates the detection result of the phase detector together.

3. The semiconductor device according to claim 1,

wherein the input data is data subjected to the spread-spectrum frequency modulation by a source of the input data, and received by the clock recovery circuit.

4. The semiconductor device according to claim 1,

wherein the input data is data having a constant frequency at a source of the input data, and received by the clock and data recovery circuit.

5. The semiconductor device according to claim 1,

wherein the frequency tracking loop comprises:

a first integrator that integrates a first control signal which is the phase detection result of the phase detector, and outputs a second control signal;

an arithmetic unit that outputs a result of adding the second control signal and a signal obtained by inverting a sign of the frequency modulation information as a third control signal; and

a pattern generator that receives the third control signal, and outputs a fourth control signal,

wherein the phase tracking loop includes a second integrator that integrates the first control signal which is the phase detection result of the phase detector together, and outputs a fifth control signal,

wherein a mixer that mixes the fourth control signal from the pattern generator and the fifth control signal from the second integrator together to output a sixth control signal is disposed at a junction of the frequency tracking loop and the phase tracking loop, and

wherein the phase interpolator interpolates the phase of the clock signal subjected to the spread-spectrum frequency modulation on the basis of the sixth control signal from the mixer.

6. The semiconductor device according to claim 1,

wherein the frequency tracking loop comprises:

a first integrator that integrates a first control signal which is the phase detection result of the phase detector together, and outputs a second control signal;

an arithmetic unit that outputs a result of adding the second control signal and a signal obtained by inverting a sign of the frequency modulation information as a third control signal; and

a pattern generator that receives the third control signal, and outputs a fourth control signal,

wherein the phase tracking loop transmits the first control signal from the phase detector,

wherein a mixer that mixes the fourth control signal from the pattern generator and the first control signal from the phase detector together to output a fifth control signal is disposed at a junction of the frequency tracking loop and the phase tracking loop,

wherein the semiconductor device further comprises a second integrator that integrates the fifth control signal together, and outputs a sixth control signal,

wherein the phase interpolator interpolates the phase of the clock signal subjected to the spread-spectrum frequency modulation on the basis of the sixth control signal from the second integrator.

7. The semiconductor device according to claim 1,

wherein the frequency tracking loop comprises:

an arithmetic unit that adds or subtracts an inclination of a spread-spectrum frequency modulation waveform to or from a first control signal which is the phase detection result of the phase detector as the frequency modulation information, and outputs an arithmetic result as a second control signal;

a first integrator that integrates the second control signal together, and outputs a third control signal; and

a pattern generator that receives the third control signal, and outputs a fourth control signal,

wherein the phase tracking loop includes a second integrator that integrates the first control signal which is the phase detection result of the phase detector together, and outputs a fifth control signal,

wherein a mixer that mixes the fourth control signal from the pattern generator and the fifth control signal from the second integrator together to output a sixth control signal is disposed at a junction of the frequency tracking loop and the phase tracking loop, and

wherein the phase interpolator interpolates the phase of the clock signal subjected to the spread-spectrum frequency modulation on the basis of the sixth control signal from the mixer.

8. The semiconductor device according to claim 7,

wherein an absolute value of a magnitude of the inclination of the spread-spectrum frequency modulation waveform is kept a constant value through a modulation period.

9. The semiconductor device according to claim 7,

wherein in a magnitude of an inclination and a direction of the inclination of the spread-spectrum frequency modulation waveform, the arithmetic unit sets a value obtained by subtracting or adding the magnitude of the inclination of the spread-spectrum frequency modulation waveform from or to the first control signal according to the direction of the inclination as the second control signal.

10. The semiconductor device according to claim 7,

wherein in a magnitude of an inclination and a direction of the inclination of the spread-spectrum frequency modulation waveform, the arithmetic unit includes a circuit that outputs +1 by the number of times corresponding to a numerator of a fraction for the magnitude of the inclination of the spread-spectrum frequency modulation waveform represented by the fraction in an elapsed clock cycle corresponding to a denominator of the fraction, and

a circuit that adds or subtracts +1 output from the circuit to or from the first control signal according to the direction of the inclination of the spread-spectrum frequency modulation waveform as the second control signal.

11. The semiconductor device according to claim 1,

wherein the frequency tracking loop comprises:

an arithmetic unit that adds or subtracts an inclination of a spread-spectrum frequency modulation waveform to or from a first control signal which is the phase detection result of the phase detector as the frequency modulation information; and

outputs an arithmetic result as a second control signal;

a first integrator that integrates the second control signal together, and outputs a third control signal; and

a pattern generator that receives the third control signal, and outputs a fourth control signal,

wherein the phase tracking loop transmits the first control signal from the phase detector,

wherein a mixer that mixes the fourth control signal from the pattern generator and the first control signal from the phase detector together to output a fifth control signal is disposed at a junction of the frequency tracking loop and the phase tracking loop,

wherein the semiconductor device further comprises a second integrator that integrates the fifth control signal together, and outputs a sixth control signal, and

wherein the phase interpolator interpolates the phase of the clock signal subjected to the spread-spectrum frequency modulation on the basis of the sixth control signal from the second integrator.

12. The semiconductor device according to claim 1,

wherein the frequency tracking loop comprises:

an arithmetic unit that adds or subtracts an inclination of a spread-spectrum frequency modulation waveform to or from a first control signal which is the phase detection result of the phase detector as the frequency modulation information, and outputs an arithmetic result as a second control signal;

a first integrator that integrates ti e second control signal together, and outputs a third control signal; and

a pattern generator that receives the third control signal, and outputs a fourth control signal,

wherein the phase tracking loop transmits the first control signal from the phase detector,

wherein a mixer that mixes the fourth control signal from the pattern generator and the first control signal which is the phase detection result of the phase detector together, and outputs a fifth control signal, and a second integrator that integrates the fifth control signal together, and outputs a sixth control signal, are disposed at a junction, of the frequency tracking loop and the phase tracking loop,

wherein the phase interpolator interpolates the phase of the clock signal subjected to the spread-spectrum frequency modulation on the basis of the sixth control signal from the second integrator,

wherein the semiconductor device further comprises a control circuit that outputs a magnitude of the inclination of the spread-spectrum frequency modulation waveform to the clock and data recovery circuit as the frequency modulation information, and

wherein the clock generator outputs a direction of the inclination of the spread-spectrum frequency modulation waveform to the arithmetic unit of the clock and data recovery circuit as the frequency modulation information.

13. The semiconductor device according to claim 12, further comprising:

at least one receiver circuit including the clock and data recovery circuit, and a serial/parallel converter circuit that converts serial data extracted by the clock and data recovery circuit into parallel data according to the extracted clock signal,

wherein one of the clock generator and one of the control circuit are provided in the at least one receiver circuit.

14. The semiconductor device according to claim 1,

wherein the clock generator includes a PLL (phase locked loop) having a controller for generating the clock signal subjected to the spread-spectrum frequency modulation.

15. The semiconductor device according to claim 1, further comprising:

at least one receiver circuit including the clock and data recovery circuit, and a serial/parallel converter circuit that converts serial data extracted by the clock and data recovery circuit into parallel data according to the extracted clock signal,

wherein the clock generator is provided in the at least one receiver circuit.

16. A semiconductor device, comprising:

a clock generator that generates a clock signal subjected to spread-spectrum frequency modulation;

a phase detector that detects an advance and a retard of a phase between input data and an extracted clock signal, and outputs a detection result as a first control signal;

a phase interpolator that receives the clock signal subjected to the spread-spectrum frequency modulation, which is generated by the clock generator, adjusts a phase of the clock signal, and supplies the clock signal to the phase detector as the extracted clock signal;

a first integrator that integrates the first control signal, and outputs a second control signal;

an arithmetic unit that receives frequency modulation information of the clock signal subjected to the spread-spectrum frequency modulation from the clock generator, and outputs a result of adding a signal obtained by inverting a sign of the frequency modulation information to the second control signal as a third control signal;

a pattern generator that receives the third control signal, and outputs a fourth control signal;

a second integrator that integrates the first control signal which is a the detection result of the phase detector together, and outputs a fifth control signal; and

a mixer that mixes the fourth control signal from the pattern generator and the fifth control signal from the second integrator together to output a sixth control signal,

wherein the phase interpolator interpolates the phase of the clock signal subjected to the spread-spectrum frequency modulation on the basis of the sixth control from the mixer.

17. A semiconductor device, comprising:

a clock generator that generates a clock signal subjected to spread-spectrum frequency modulation;

a phase detector that detects an advance and a retard of a phase between input data and an extracted clock signal, and outputs a detection result as a first control signal;

a phase interpolator that receives the clock signal subjected to the spread-spectrum frequency modulation, which is generated by the clock generator, adjusts a phase of the clock signal, and supplies the clock signal to the phase detector as the extracted clock signal;

an arithmetic unit that receives a direction of an inclination of a spread-spectrum frequency modulation waveform of the clock signal from the clock generator, and outputs a result of adding or subtracting a magnitude of the inclination of the spread-spectrum frequency modulation waveform to or from the first control signal on the basis of the direction of the inclination of the spread-spectrum frequency modulation waveform as a second control signal;

a first integrator that integrates the second control signal together, and outputs a third control signal;

a pattern generator that receives the third control signal, and outputs a fourth control signal;

a mixer that mixes the fourth control signal from the pattern generator and the first control signal from the phase detector together, and outputs a fifth control signal; and

a second integrator that integrates the fifth control signal from the mixer together, and outputs a sixth control signal,

wherein the phase interpolator interpolates the phase of the clock signal subjected to the spread-spectrum frequency modulation on the basis of the sixth control signal from the second integrator,

wherein the semiconductor device further comprises a control circuit that outputs the magnitude of the inclination of the spread-spectrum frequency modulation waveform to a clock and data recovery circuit, and

wherein the clock generator outputs the direction of the inclination of the spread-spectrum frequency modulation waveform to the arithmetic unit of the clock and data recovery circuit.

18. The semiconductor device according to claim 17,

wherein an absolute value of the magnitude of the inclination of the spread-spectrum frequency modulation waveform is kept a constant value through a modulation period.

19. The semiconductor device according to claim 18,

wherein the arithmetic unit includes a circuit that outputs +1 by the number of times corresponding to a numerator of a fraction for the magnitude of the inclination of the spread-spectem frequency modulation waveform represented by the fraction in an elapsed clock cycle corresponding to a denominator of the fraction, and

a circuit that adds or subtracts +1 output from the circuit to or from the first control signal according to the direction of the inclination as the second control signal.

20. The semiconductor device according to claim 17, further comprising:

at least one receiver circuit including the dock and data recovery circuit, and a serial/parallel converter circuit that converts serial data extracted by the clock and data recovery circuit into parallel data according to the extracted clock signal,

wherein one of the clock generator and one of the control circuit are provided in the at least one receiver circuit.