Methods and systems for high bandwidth chip-to-chip communications interface
First Claim
Patent Images
1. A transceiver comprising:
- an interconnection between at least a first and a second integrated circuit device, the interconnection comprising at least one interconnection wire group, wherein each interconnection wire group is a wire group for communicating signals representing a code word of a vector signaling code;
an encoder that converts a received transmit data word to a transmit code word of a vector signaling code;
a transmit driver that emits physical signals on wires of the interconnection wire group that correspond to elements of the transmit code word;
a receiver circuit that detects physical signals on the interconnection wires as elements of a received code word of a vector signaling code comprising a plurality of signal summers each configured to sum physical signals on two selected wires and a plurality of comparators to compare outputs of the signal summers and to generate a decoded output representing a receive data word.
1 Assignment
0 Petitions
Accused Products
Abstract
Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.
60 Citations
10 Claims
-
1. A transceiver comprising:
-
an interconnection between at least a first and a second integrated circuit device, the interconnection comprising at least one interconnection wire group, wherein each interconnection wire group is a wire group for communicating signals representing a code word of a vector signaling code; an encoder that converts a received transmit data word to a transmit code word of a vector signaling code; a transmit driver that emits physical signals on wires of the interconnection wire group that correspond to elements of the transmit code word; a receiver circuit that detects physical signals on the interconnection wires as elements of a received code word of a vector signaling code comprising a plurality of signal summers each configured to sum physical signals on two selected wires and a plurality of comparators to compare outputs of the signal summers and to generate a decoded output representing a receive data word. - View Dependent Claims (2, 3, 4)
-
-
5. An apparatus comprising:
-
a set of four wires for carrying signals associated with a vector signaling code; a set of three comparator circuits, each comparator circuit connected to all four wires of the set of four wires, and each comparator circuit having a two-input comparator providing a comparison output; each comparator circuit of the set of comparator circuits further comprising two adder circuits, each adder circuit connected to an input of the respective two-input comparator, and each adder circuit is connected to a globally unique pair of wires selected from the set of four wires. - View Dependent Claims (6, 7, 8)
-
-
9. A method comprising:
-
receiving at an integrated circuit device a vector signaling code word comprising symbols selected from an alphabet of three or more values; detecting the at least one vector signaling code word by at least one comparison of a sum of physical signals on two selected wires and a sum of physical signals on a remaining two wires; wherein each detection comparison represents one bit of a received binary data word corresponding to a transmitted data word, the received binary data word being output for use by the receiving integrated circuit device. - View Dependent Claims (10)
-
Specification