High-speed parallel decision feedback equalizer

• US 9,071,479 B2
• Filed: 08/24/2012
• Issued: 06/30/2015
• Est. Priority Date: 08/24/2012
• Status: Active Grant

• Current Assignee: Credo Technology Group Limited (Credo Technology Group Holding Ltd.)
• Original Assignee: Credo Semiconductor (Hong Kong) Limited
• Inventors: Qian, Haoli, Lam, Yat-tung, He, Runsheng
• Primary Examiner(s): Aghdam, Freshteh N
• Application Number:
  US13/594,595
• Publication Number:
  US 20140056346A1
• Time in Patent Office: 1,040 Days
• Field of Search: 375/229, 375/233, 375/316, 375/324
• US Class Current: 1/1
• CPC Class Codes: H04B 10/6971 using equalisation
• CPC Class Codes: H04L 2025/03356 Baseband transmission
• CPC Class Codes: H04L 2025/03496 as a prediction filter
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules. One illustrative embodiment includes a front end filter to reduce leading intersymbol interference in a receive signal; a serial-to-parallel converter and at least one pre-compensation unit that together convert the filtered signal into grouped sets of tentative decisions, the sets in each group being made available in parallel; a set of pipelined DFE multiplexer units to select a contingent symbol decision from each set of tentative decisions to form groups of contingent symbol decisions based on a presumed sequence of preceding symbol decisions; and an output multiplexer that chooses, based on preceding symbol decisions, one of said groups of contingent symbol decisions.

Claims

1. A high speed equalization method that comprises:

deriving at each of multiple consecutive time intervals a set of tentative decisions, each tentative decision accounting for a respective degree of trailing intersymbol interference;

forming a parallel group from a series of said sets of tentative decisions;

applying the parallel group to a set of pipelined DFE multiplexer units, each said unit selecting a contingent symbol decision from each set of tentative decisions in the group to form a group of contingent symbol decisions based on a different presumed sequence of preceding symbol decisions; and

choosing, based on an actual sequence of preceding symbol decisions, one of said groups of contingent symbol decisions as a group of actual symbol decisions.

2. The method of claim 1, wherein said deriving includes:

minimizing leading intersymbol interference with a front end filter, thereby providing a filtered input signal; and

distributing the filtered input signal across a set of paths, each path compensating the filtered input signal for a respective degree of trailing intersymbol interference.

3. The method of claim 1, wherein the set of tentative decisions and the set of pipelined DFE multiplexer units each have a cardinality of 2^N, where N is a number of preceding symbols causing trailing intersymbol interference.

4. The method of claim 1, wherein each group has a cardinality of P, wherein P is a finite integer parallelization factor at least equal to 2.

5. The method of claim 1, further comprising latching the group of actual symbol decisions.

6. The method of claim 1, further comprising applying N most recent actual symbol decisions to a multiplexer that performs said choosing, where N is a number of preceding symbols causing trailing intersymbol interference.

7. A high speed equalizer that comprises:

a front end filter that reduces leading intersymbol interference in a receive signal to provide a filtered signal;

a serial-to-parallel converter and at least one precompensation unit that together convert the filtered signal into grouped sets of tentative decisions, the sets in each group being made available in parallel;

a set of pipelined DFE multiplexer units, each multiplexer unit selecting a contingent symbol decision from each set of tentative decisions in each group to form groups of contingent symbol decisions based on a different presumed sequence of preceding symbol decisions; and

an output multiplexer that chooses, based on an actual sequence of preceding symbol decisions, one of said groups of contingent symbol decisions as a group of actual symbol decisions.

8. The equalizer of claim 7, further comprising an output latch that holds the actual symbol decisions for group interval delay.

9. The equalizer of claim 7, wherein the precompensation unit derives digital decisions from analog signals.

10. The equalizer of claim 9, wherein the precompensation unit outputs decisions at a rate in excess of 10 GHz.

11. The equalizer of claim 7, wherein the front end filter, serial-to-parallel converter, and precompensation unit are implemented with digital circuit elements.

12. The equalizer of claim 7, wherein the set of tentative decisions and the set of pipelined DFE multiplexer units each have a cardinality of 2^N, where N is a number of preceding symbols causing trailing intersymbol interference, and wherein each group has a cardinality of P, wherein P is a finite integer parallelization factor at least equal to 2.

13. A channel interface module that comprises a receiver having:

a sensor that converts receive channel signals into electrical signals;

a front end filter that enhances the signal-to-noise ratio of the electrical signals;

at least one precompensation unit and a serial-to-parallel converter that together produce groups of tentative decision sets, the sets in each group being made available in parallel;

a set of multiplexer units that each operate on each group to obtain a group of contingent decisions based on a different presumed sequence of preceding symbol decisions;

an output multiplexer that, based on actual preceding symbol decisions, chooses a group of actual symbol decisions from the groups of contingent decisions; and

a device interface that provides a host node with a received data stream derived from the group of actual symbol decisions.

14. The module of claim 13, further comprising a transmitter that receives a transmit data stream from said device interface and converts said transmit data stream to a transmit channel signal.

15. The module of claim 14, wherein the received data stream carries at least 10 Gbit/s.

16. The module of claim 13, wherein the receiver further includes an output latch that holds the group of actual symbol decisions for group interval delay.

17. The module of claim 13, wherein the tentative decision sets and the set of multiplexer units each have a cardinality of 2^N, where N is a number of preceding symbols causing trailing intersymbol interference.

18. The module of claim 13, wherein the output multiplexer employs N most recent actual symbol decisions from a preceding group of actual symbol decisions to perform said choosing, where N is a number of preceding symbols causing trailing intersymbol interference.

19. The module of claim 17, wherein each group has a cardinality of P, wherein P is finite integer parallelization factor at least equal to 2.

20. The module of claim 19, wherein P is greater than N.

21. The module of claim 13, wherein the transmit and receive channel signals are optical signals.

22. The module of claim 13, wherein the channel is an information storage medium.

23. The module of claim 13, wherein the transmit and receive channel signals are electromagnetic signals conveyed via twisted wire pair, coaxial cable, or backplane transmission lines.