General input/output architecture, protocol and related methods to implement flow control

• US 9,071,528 B2
• Filed: 12/28/2012
• Issued: 06/30/2015
• Est. Priority Date: 08/24/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Harriman, David, Fanning, Blaise, Lee, David
• Primary Examiner(s): Baturay, Alicia
• Application Number:
  US13/730,024
• Publication Number:
  US 20130254451A1
• Time in Patent Office: 914 Days
• Field of Search: 709/233
• US Class Current: 1/1
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4252 using a handshaking protocol
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 13/4269 using a handshaking protocol, e.g. Centronics connection
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes

Abstract

An enhanced general input/output communication architecture, protocol and related methods are presented.

Claims

1. An apparatus comprising:

a device to;

receive a packet from a differential, point-to-point serial data link;

identify, from a traffic class field in the packet, a traffic class associated with the packet;

identify a mapping of the traffic class to a virtual channel;

send the packet using the virtual channel; and

generate physical layer information for the packet to include an identification of the virtual channel.

2. The apparatus of claim 1, wherein the link comprises at least one of a physical layer to support a PCI-based protocol layer and a physical layer including one or more other protocols.

3. The apparatus of claim 1, wherein the link comprises a PCI-based protocol-compliant data link.

4. The apparatus of claim 1, wherein the traffic class field is to be included in transaction layer information of the packet.

5. The apparatus of claim 1, wherein the virtual channel is one of a plurality of virtual channels.

6. The apparatus of claim 5, wherein the plurality of virtual channels includes at least eight virtual channels.

7. The apparatus of claim 5, wherein the plurality of virtual channels includes at least one virtual channel to handle isochronous traffic.

8. The apparatus of claim 5, wherein the plurality of virtual channels are channels supported by a particular system component.

9. The apparatus of claim 5, wherein the plurality of virtual channels includes a default virtual channel.

10. An apparatus comprising:

a root complex to;

identify a traffic class of a packet from transaction layer information of the packet;

use a virtual channel capability structure to identify a particular virtual channel associated with the traffic class, wherein the particular virtual channel is to be included in a set of at least eight supported virtual channels, the set of virtual channels to include a default virtual channel, and wherein each virtual channel is to comprise a respective one of a plurality of independent logical data flows for a differential, point-to-point serial data link;

assemble physical layer information for the packet to include an identification of the particular virtual channel; and

send the packet, to include transaction layer information to identify the traffic class and the physical layer information, over the link to a device.

11. A method comprising:

receiving a packet over a differential, point-to-point serial data link;

identifying, from a traffic class field in the packet, a traffic class associated with the packet;

identifying a virtual channel associated with the traffic class from a mapping of traffic classes to virtual channels;

sending the packet using the virtual channel; and

generating physical layer information for the packet to include an identification of the virtual channel.

12. The method of claim 11, wherein the data link provides support for full-duplex communication.

13. The method of claim 11, wherein the packet is received from a first device and sent to a second device.

14. The method of claim 11, wherein the packet is sent to include an identification of the traffic class and the physical layer information.

15. The method of claim 11, wherein the virtual channel is a particular one of a plurality of virtual channels.

16. A system comprising:

an interconnect, wherein the interconnect comprises a serial point-to-point data link;

a data structure mapping traffic classes to virtual channels;

a first device; and

a second device communicatively coupled to the first device using the interconnect, the second device to;

identify, from a traffic class field in the packet, a traffic class associated with the packet;

identify a virtual channel associated with the traffic class from the data structure;

send the packet to the first device using the virtual channel; and

generate physical layer information for the packet to include an identification of the virtual channel.

17. The system of claim 16, wherein the interconnect comprises a general input/output interconnect architecture.

18. The system of claim 16, further comprising a third device, wherein the packet is received from a third device.

19. The system of claim 16, wherein the second device comprises a switch.

20. The system of claim 16, wherein the second device comprises a root complex.