Methods and devices for treating and processing data

• US 9,075,605 B2
• Filed: 10/17/2012
• Issued: 07/07/2015
• Est. Priority Date: 03/05/2001
• Status: Expired due to Term

• Current Assignee: PACT XPP Schweiz AG
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin, Baumgarte, Volker
• Primary Examiner(s): Elamin, M
• Application Number:
  US13/653,639
• Publication Number:
  US 20130042137A1
• Time in Patent Office: 993 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Claims

1. A method for operating a multiprocessor system comprising a plurality of data processing cells, each of the plurality of data processing units (a) including at least one Arithmetic Logic Unit (ALU) and a register unit and (b) being adapted for sequentially processing data, the method comprising:

the multiprocessor system setting a clock frequency, of at least a part of the multiprocessor system to a minimum in accordance with a number of pending operations of a first processor;

the multiprocessor system subsequently increasing the clock frequency of the at least the part of the multiprocessor system to a maximum in accordance with a number of pending operations of a second processor; and

the multiprocessor system subsequently reducing the clock frequency of the at least the part of the multiprocessor system in accordance with (a) an operating temperature threshold preventing over-temperature and (b) a hysteresis characteristic.

2. The method of claim 1 wherein:

said clock frequency is determined in part by processor voltage.

3. The method of claim 1 wherein:

said clock frequency is determined in part by available power.

4. The method of claim 1 wherein:

said clock frequency is determined in part by a user setting.

5. The method of claim 1 wherein:

said clock frequency is determined in part by available power and a user setting.

6. The method of claim 1 wherein:

said number of pending operations is determined at by the fill level of one or more buffers.