Digital fast dB to gain multiplier for envelope tracking systems
First Claim
Patent Images
1. A digital log gain to digital linear gain multiplier for an envelope tracking system comprising:
- a log gain splitter including a floor function circuit adapted to split a log gain value into an integer log part that is less than or equal to the log gain value, and a remainder log part, wherein the floor function circuit outputs the integer log part in response to a scaled log gain value received by the floor function that outputs the integer log part; and
an adder circuit coupled to the floor function circuit that outputs the remainder log part by summing the log gain value with the negative of the integer log part;
a binary anti-log circuit adapted to receive the integer log part from the log gain splitter and output a binary anti-log value of the integer log part;
a log-to-linear look up table (LUT) adapted to receive the remainder log part from the adder circuit and output a LUT value corresponding to the remainder log part; and
a converter multiply circuit adapted to multiply the binary anti-log value from the binary anti-log circuit by the LUT value to produce a linear gain value; and
a gain multiply circuit adapted to multiply a digital signal having a sample rate of at least 52 MHz by the linear gain value to output a gain-enhanced digital signal.
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Abstract
A digital log gain to digital linear gain multiplier is disclosed. The digital log gain to digital linear gain multiplier includes a log gain splitter adapted to split a log gain input into an integer log part and a remainder log part. A log scale-to-linear scale converter is adapted to output a linear gain value in response to the integer log part and the remainder log part. A gain multiply circuit is adapted to multiply a digital signal by the linear gain value to output a gain-enhanced digital signal.
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Citations
17 Claims
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1. A digital log gain to digital linear gain multiplier for an envelope tracking system comprising:
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a log gain splitter including a floor function circuit adapted to split a log gain value into an integer log part that is less than or equal to the log gain value, and a remainder log part, wherein the floor function circuit outputs the integer log part in response to a scaled log gain value received by the floor function that outputs the integer log part; and
an adder circuit coupled to the floor function circuit that outputs the remainder log part by summing the log gain value with the negative of the integer log part;a binary anti-log circuit adapted to receive the integer log part from the log gain splitter and output a binary anti-log value of the integer log part; a log-to-linear look up table (LUT) adapted to receive the remainder log part from the adder circuit and output a LUT value corresponding to the remainder log part; and a converter multiply circuit adapted to multiply the binary anti-log value from the binary anti-log circuit by the LUT value to produce a linear gain value; and a gain multiply circuit adapted to multiply a digital signal having a sample rate of at least 52 MHz by the linear gain value to output a gain-enhanced digital signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An envelope tracking system comprising:
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a power amplifier module (PAM); a fast switch mode power supply (SMPS) converter adapted to supply modulated power to the PAM in response to an envelope tracking signal (ETS) that is derived from a digital signal that is gain-enhanced and having a sample rate of at least 52 MHz; an envelope tracking signal (ETS) generator adapted to drive the SMPS converter with the ETS; and a digital log gain to digital linear gain multiplier for adjusting the gain of the digital signal, comprising; a log gain splitter including a floor function circuit adapted to split a log gain value into an integer log part that is less than or equal to the log gain value, and a remainder log part, wherein the floor function circuit outputs the integer log part in response to a scaled log gain value received by the floor function that outputs the integer log part; and
an adder circuit coupled to the floor function circuit that outputs the remainder log part by summing the log gain value with the negative of the integer log part;a binary anti-log circuit adapted to receive the integer log part from the log gain splitter and output a binary anti-log value of the integer log part; a log-to-linear look up table (LUT) adapted to receive the remainder log part from the adder circuit and output an LUT value corresponding to the remainder log part; and a converter multiply circuit adapted to multiply the binary anti-log value from the binary anti-log circuit by the LUT value to produce a linear gain value; and a gain multiply circuit adapted to multiply the digital signal having a sample rate of at least 52 MHz by the linear gain value to output the gain-enhanced digital signal. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method of adjusting a gain of a digital signal for an envelope tracking system having a power amplifier module (PAM), and a fast switch mode power supply (SMPS) converter adapted to supply modulated power to the PAM in response to an envelope tracking signal (ETS), comprising:
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splitting a log gain value by way of a log gain splitter into an integer log part that is less than or equal to the log gain value, and a remainder log part, wherein a floor function circuit outputs the integer log part in response to a scaled log gain value received by the floor function that outputs the integer log part; and
outputting the remainder log part received from an adder circuit coupled to the floor function circuit by summing the log gain value with the negative of the integer log part;outputting a binary anti-log value of the integer log part by way of a binary anti-log circuit in response to receiving the integer log part from the log gain splitter; outputting by way of a log-to-linear LUT an LUT value corresponding to the remainder log part in response to receiving the remainder log part from the adder circuit; multiplying the binary anti-log value from the binary anti-log circuit by the LUT value to produce a linear gain value; multiplying a digital signal having a sample rate of at least 52 MHz by the linear gain value by way of a converter multiply circuit; outputting a resulting gain-enhanced digital signal by way of a gain multiply circuit; deriving the ETS from the gain-enhanced digital signal; and driving the SMPS converter with the ETS. - View Dependent Claims (14, 15, 16, 17)
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Specification