Distributed interconnect bus apparatus
First Claim
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1. An apparatus for enabling a distributed connection of peripheral devices, comprising:
- a first bridge coupled to a root component of a PCI Express (PCIe), the first bridge comprising;
a first acknowledgment (ACK) termination configured as a data link layer of the PCIe bus; and
a first flow control mechanism,the first ACK termination being adapted to send, to the root component, an ACK signal upon reception of each PCIe transaction layer packet; and
a second bridge communicatively coupled to the first bridge over a distributed medium, wherein;
the first bridge and the second bridge are configured to exchange PCIe transaction layer packets over the distributed medium,the second bridge is also coupled to an endpoint component of the PCIe bus,the second bridge comprises a second ACK termination and a second flow control mechanism,the second ACK termination is configured to send, to the endpoint component, an ACK signal upon reception of each transaction layer packet received from the endpoint component,the second ACK termination is configured as a data link layer of the PCIe bus, andthe first flow control mechanism and the second flow control mechanism are each configured to store multiple PCIe transaction layer packets to compensate for a transmission delay of PCIe transaction layer packets over the distributed medium between the first and second bridge.
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Abstract
A distributed interconnect bus apparatus for connecting peripheral devices. The apparatus can be utilized to wirelessly connect peripheral devices or to allow the connectivity of such devices over a network. The apparatus includes a first bridge coupled to a root component of an interconnect bus; and a second bridge coupled to an endpoint component of an interconnect bus. The apparatus may further include an acknowledgment (ACK) termination for generating at least an ACK signal; and a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.
66 Citations
17 Claims
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1. An apparatus for enabling a distributed connection of peripheral devices, comprising:
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a first bridge coupled to a root component of a PCI Express (PCIe), the first bridge comprising; a first acknowledgment (ACK) termination configured as a data link layer of the PCIe bus; and a first flow control mechanism, the first ACK termination being adapted to send, to the root component, an ACK signal upon reception of each PCIe transaction layer packet; and a second bridge communicatively coupled to the first bridge over a distributed medium, wherein; the first bridge and the second bridge are configured to exchange PCIe transaction layer packets over the distributed medium, the second bridge is also coupled to an endpoint component of the PCIe bus, the second bridge comprises a second ACK termination and a second flow control mechanism, the second ACK termination is configured to send, to the endpoint component, an ACK signal upon reception of each transaction layer packet received from the endpoint component, the second ACK termination is configured as a data link layer of the PCIe bus, and the first flow control mechanism and the second flow control mechanism are each configured to store multiple PCIe transaction layer packets to compensate for a transmission delay of PCIe transaction layer packets over the distributed medium between the first and second bridge. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for enabling a distributed connection of peripheral devices, comprising:
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sending, from a first ACK termination of a first bridge, to a root component coupled to the first bridge, a first ACK signal upon reception of each PCI express (PCIe) transaction layer packet sent from the root component during a first PCIe transaction; storing, at a first flow control mechanism of the first bridge, each PCIe transaction layer packet received from the root component during the first PCIe transaction to compensate for a transmission delay of PCIe transaction layer packets over a distributed medium between the first and a second bridge; sending, from a second ACK termination of the second bridge, to an endpoint component coupled to the second bridge, a second ACK signal upon reception of each PCIe transaction layer packet received from the endpoint component during the first PCIe transaction; storing, at the second flow control mechanism, each PCIe transaction layer packet received from the endpoint component during the first PCIe transaction to compensate for a transmission delay of PCIe transaction layer packets over the distributed medium between the first and second bridge; and exchanging the received PCIe transaction layer packets between the first bridge and the second bridge communicatively coupled over the distributed medium. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A distributed interconnect bus, comprising:
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one or more wireless transceivers; a first bridge coupled to a root component of a PCI Express (PCIe) bus, the first bridge comprising; a first acknowledgment (ACK) termination configured as a data link layer of the PCIe bus; and a first flow control mechanism; and a second bridge communicatively coupled to the first bridge, wherein; the first bridge and the second bridge are configured to exchange PCIe transaction layer packets via the wireless transceivers, the first ACK termination is adapted to send, to the root component, an ACK signal upon reception of each PCIe transaction layer packet the second bridge is also coupled to an endpoint component of the PCIe bus, the second bridge comprises a second ACK termination and a second flow control mechanism, the second ACK termination is configured to send to the endpoint component, an ACK signal upon reception of each transaction layer packet received from the endpoint component, the second ACK termination is configured as a data link layer of the PCIe bus, and the first flow control mechanism and the second flow control mechanism are each configured to store multiple PCIe transaction layer packets to compensate for a transmission delay of PCIe transaction layer packets over a distributed medium between the first and second bridge.
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Specification