×

System and method of predicting problematic areas for lithography in a circuit design

  • US 9,075,944 B2
  • Filed: 06/26/2013
  • Issued: 07/07/2015
  • Est. Priority Date: 04/17/2008
  • Status: Expired due to Fees
First Claim
Patent Images

1. A method, comprising:

  • by a processor;

    calculating planes of focus for exposure for one or more tiles of a modeled wafer that best fits modeled surface height data for a predetermined number of values within a slit;

    calculating distances of each of the tiles within the slit to each of the calculated planes along an axis of illumination;

    calculating an average focus offset from the calculated distances; and

    identifying tiles with an average focus offset that is outside of a certain specification range which is related to a depth of focus for the lithography process.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×