System and method of predicting problematic areas for lithography in a circuit design

• US 9,075,944 B2
• Filed: 06/26/2013
• Issued: 07/07/2015
• Est. Priority Date: 04/17/2008
• Status: Expired due to Fees

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Brunner, Timothy A., Greco, Stephen E., Liegl, Bernhard R., Xiang, Hua
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US13/928,205
• Publication Number:
  US 20130286370A1
• Time in Patent Office: 741 Days
• Field of Search: 716/50, 716/51, 716/52, 716/53, 716/54, 716/55, 716/56
• US Class Current: 1/1
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Claims

1. A method, comprising:

by a processor;

calculating planes of focus for exposure for one or more tiles of a modeled wafer that best fits modeled surface height data for a predetermined number of values within a slit;

calculating distances of each of the tiles within the slit to each of the calculated planes along an axis of illumination;

calculating an average focus offset from the calculated distances; and

identifying tiles with an average focus offset that is outside of a certain specification range which is related to a depth of focus for the lithography process.

2. The method of claim 1, wherein the identified tiles are identified as design areas which will be prone to lithography problems at subsequent lithography levels.

3. The method of claim 1, wherein the identified tiles are fixed by changing a chip design by adjusting at least one of metal patterns and densities.

4. The method of claim 1, wherein the identified tiles are fixed by changing a chip design by adjusting at least one of metal patterns and densities in other tiles at a level at which a prediction is performed or at one or more underlying metal levels.

5. The method of claim 1, further comprising repeating the steps of claim 1.

6. The method of claim 1, wherein critical images are removed in the identified tiles at a higher level.

7. The method of claim 1, wherein the calculating the planes comprises finding a plane which minimizes a sum of the orthogonal distances or a sum of the squares of the orthogonal distances from the plane.

8. A memory or storage system storing computer program code that when executed by a processor, causes the processor to perform a method, the method comprising:

calculating planes of focus for exposure for one or more tiles of a modeled wafer that best fits modeled surface height data for a predetermined number of values within a slit;

calculating distances of each of the tiles within the slit to each of the calculated planes along an axis of illumination;

calculating an average focus offset from the calculated distances; and

identifying tiles with an average focus offset that is outside of a certain specification range which is related to a depth of focus for the lithography process.

9. The memory or storage system of claim 8, wherein the identified tiles are identified as design areas which will be prone to lithography problems at subsequent lithography levels.

10. The memory or storage system of claim 8, wherein the identified tiles are fixed by changing a chip design by adjusting at least one of metal patterns and densities.

11. The memory or storage system of claim 8, wherein the identified tiles are fixed by changing a chip design by adjusting at least one of metal patterns and densities in other tiles at a level at which a prediction is performed or at one or more underlying metal levels.

12. The memory or storage system of claim 8, wherein the method further comprises repeating the steps of claim 8.

13. The memory or storage system of claim 8, wherein critical images are removed in the identified tiles at a higher level.

14. The memory or storage system of claim 8, wherein the calculating the planes comprise finding a plane which minimizes a sum of the orthogonal distances or a sum of the squares of the orthogonal distances from the plane.