Active matrix substrate, liquid crystal panel, liquid crystal display device, television receiver

• US 9,076,394 B2
• Filed: 12/08/2010
• Issued: 07/07/2015
• Est. Priority Date: 02/15/2010
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Saitoh, Yuhichi
• Primary Examiner(s): HOFFNER, LINH NGUYEN
• Application Number:
  US13/577,700
• Publication Number:
  US 20120300133A1
• Time in Patent Office: 1,672 Days
• Field of Search: 345/100
• US Class Current: 1/1
• CPC Class Codes: G06F 3/038 Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0447 for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2320/028 by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Abstract

An active matrix substrate of the present invention includes: data signal lines; scanning signal lines (GLi); transistors connected with the data signal lines and the scanning signal lines (GLi); and retention capacitor lines (CSLi). One pixel region includes a plurality of pixel electrodes. A CS driver (46) for outputting a retention capacitor line signal to drive the retention capacitor lines is formed monolithically. In one pixel region, a pixel electrode and a retention capacitor line corresponding to the pixel electrode forms a retention capacitor therebetween. This allows the liquid crystal display device based on a pixel-division system to have a liquid crystal panel with a narrower frame.

Claims

1. An active matrix substrate, comprising:

data signal lines;

scanning signal lines;

transistors connected with the data signal lines and the scanning signal lines; and

retention capacitor lines,

one pixel region including a plurality of pixel electrodes,

the active matrix substrate further comprising a retention capacitor line driving circuit configured to output a retention capacitor line signal to drive the retention capacitor lines, the retention capacitor line driving circuit being defined by a single monolithic member, and

in one pixel region, at least one pixel electrode of the plurality of pixel electrodes and a retention capacitor line corresponding to said at least one pixel electrode defining a retention capacitor therebetween, wherein

the retention capacitor line driving circuit includes a plurality of retention capacitor line driving internal circuits each supplying the retention capacitor line signal to the retention capacitor line,

each of the plurality of retention capacitor line driving internal circuits is respectively provided to every other one of the retention capacitor lines, and

one of two adjacent ones of the plurality of retention capacitor lines receives the retention capacitor line signal from the retention capacitor line driving internal circuit, and another one of the two adjacent ones of the plurality of retention capacitor lines receives a signal from a signal source provided outside the retention capacitor line driving internal circuit.

2. The active matrix substrate as set forth in claim 1, wherein the retention capacitor line driving circuit is defined monolithically on a glass substrate.

3. The active matrix substrate as set forth in claim 1, wherein the retention capacitor line driving circuit and a scanning signal line driving circuit are defined monolithically.

4. The active matrix substrate as set forth in claim 1, wherein the retention capacitor line driving circuit supplies the retention capacitor line signal to the retention capacitor line which defines a retention capacitor with the pixel electrode, so that a pixel potential written in the pixel electrode from the data signal line is changed in a direction corresponding to a polarity of the pixel potential.

5. The active matrix substrate as set forth in claim 1, wherein in one pixel region, the plurality of pixel electrodes and retention capacitor lines respectively corresponding to the plurality of pixel electrodes define different retention capacitors therebetween.

6. The active matrix substrate as set forth in claim 1, wherein

one pixel region includes a first pixel electrode, a second pixel electrode, a first transistor, and a second transistor, the first transistor and the second transistor being connected with the scanning signal line, and

the first pixel electrode is connected with the data signal line via the first transistor and defines a first retention capacitor with the retention capacitor line, and the second pixel electrode is connected with the data signal line via the second transistor and defines a second retention capacitor with the retention capacitor line.

7. The active matrix substrate as set forth in claim 1, wherein

a first pixel region and a second pixel region are aligned in this order in a column direction which is a direction in which the data signal lines are extended, and in each of the first pixel region and the second pixel region, a first pixel electrode and a second pixel electrode are aligned in this order in the column direction, and

the second pixel electrode in the first pixel region and the first pixel electrode in the second pixel region are adjacent to each other, and define retention capacitors with a same retention capacitor line.

8. The active matrix substrate as set forth in claim 1, wherein

each of the retention capacitor line driving internal circuits receives a retention target signal,

a retention capacitor line driving internal circuit corresponding to a certain pixel receives and retains the retention target signal when a scanning signal supplied to a scanning signal line corresponding to a pixel positioned posterior to the certain pixel becomes active, and

an output from the retention capacitor line driving internal circuit corresponding to the certain pixel is supplied as the retention capacitor line signal to a retention capacitor line corresponding to the certain pixel.

9. The active matrix substrate as set forth in claim 1, wherein

each of the retention capacitor line driving internal circuits receives a retention target signal,

a retention capacitor line driving internal circuit corresponding to a certain pixel receives and retains the retention target signal when a scanning signal supplied to a scanning signal line corresponding to a pixel positioned posterior to the certain pixel becomes active, and

an output from the retention capacitor line driving internal circuit corresponding to the certain pixel is supplied as the retention capacitor line signal to a retention capacitor line corresponding to the certain pixel and a retention capacitor line corresponding to a pixel positioned anterior to the certain pixel.

10. The active matrix substrate as set forth in claim 9, wherein

a retention capacitor line signal from a retention capacitor line driving internal circuit at k-stage is supplied to a retention capacitor line in (k−

2)-th row and a retention capacitor line in k-th row,

a signal from an external signal source is supplied to a retention capacitor line in (k−

3)-th row and a retention capacitor line in (k−

1)-th row, and

a scanning signal to be supplied to a scanning signal line in (k+3)-th row is inputted to the retention capacitor line driving internal circuit at k-stage.

11. The active matrix substrate as set forth in claim 1, wherein

each of the retention capacitor line driving internal circuits receives a retention target signal,

a retention capacitor line driving internal circuit corresponding to a certain pixel includes

a first input section to which a scanning signal to be supplied to a scanning signal line corresponding to a pixel positioned posterior to the certain pixel is inputted,

a second input section to which the retention target signal is inputted,

a third input section to which the retention target signal is inputted, and

an output section configured to output the retention capacitor line signal,

in a case where a potential of the retention target signal inputted to the second input section is in a high level when the scanning signal inputted to the first input section becomes active, the retention capacitor line signal with a high level potential is outputted,

in a case where a potential of the retention target signal inputted to the third input section is in a high level when the scanning signal inputted to the first input section becomes active, the retention capacitor line signal with a low level potential is outputted, and

while the scanning signal inputted to the first input section is not active, the potential of the retention target signal inputted to the second input section and/or the third input section is retained.

12. The active matrix substrate as set forth in claim 1, wherein

each of the retention capacitor line driving internal circuits receives a retention target signal,

a retention capacitor line driving internal circuit corresponding to a certain pixel includes

a first input section to which a scanning signal to be supplied to a scanning signal line corresponding to a pixel positioned posterior to the certain pixel is inputted,

a second input section to which the retention target signal is inputted,

a third input section to which the retention target signal is inputted, and

an output section configured to output the retention capacitor line signal,

in a case where a potential of the retention target signal inputted to the second input section is in a high level when the scanning signal inputted to the first input section becomes active, the retention capacitor line signal with a high level potential is outputted,

in a case where a potential of the retention target signal inputted to the third input section is in a high level when the scanning signal inputted to the first input section becomes active, the retention capacitor line signal with a low level potential is outputted, and

when the scanning signal inputted to the first input section becomes inactive and when a scanning signal supplied to a scanning signal line corresponding to a pixel positioned posterior to the pixel positioned posterior to the certain pixel becomes active, the potential of the retention target signal inputted to and retained in the second input section and/or the third input section is reduced.

13. The active matrix substrate as set forth in claim 12, further comprising a fourth input section and a fifth input section to each of which a second retention target signal is inputted,

in a case where a potential of the retention target signal inputted to the second input section is in a high level when the scanning signal inputted to the first input section becomes active, the retention capacitor line signal with a high level potential being outputted,

in a case where a potential of the retention target signal inputted to the third input section is in a high level when the scanning signal inputted to the first input section becomes active, the retention capacitor line signal with a low level potential being outputted, and

when the scanning signal inputted to the first input section becomes inactive and when a scanning signal supplied to a scanning signal line corresponding to a pixel positioned posterior to the pixel positioned posterior to the certain pixel becomes active, the second retention target signal is inputted to the fourth input section and/or the fifth input section, so that the potential of the retention target signal inputted to and retained in the second input section and/or the third input section is reduced.

14. The active matrix substrate as set forth in claim 1, wherein

pixel regions each including a plurality of pixel electrodes are aligned in a column direction which is a direction in which the data signal lines are extended and in a row direction, a first data signal line and a second data signal line are provided for each column of the pixel regions and one scanning signal line is provided for each row of the pixel regions, and

a data signal line connected via a transistor with the plurality of pixel electrodes in one of two pixel regions adjacent in the column direction is different from a data signal line connected via a transistor with the plurality of pixel electrodes in the other of the two pixel regions.

15. The active matrix substrate as set forth in claim 14, wherein adjacent two scanning signal lines are selected simultaneously.

16. The active matrix substrate as set forth in claim 14, wherein data signals with opposite polarities are supplied to the first data signal line and the second data signal line, respectively.

17. The active matrix substrate as set forth in claim 1, wherein

one pixel region includes two pixel electrodes, and

one of the two pixel electrodes surrounds the other of the two pixel electrodes.

18. The active matrix substrate as set forth in claim 17, wherein

one pixel region includes two sub-pixels, and

a sub-pixel including said one of the two pixel electrodes serves as a dark sub-pixel with relatively low luminance, and a sub-pixel including said the other of the two pixel electrodes serves as a bright sub-pixel with relatively high luminance.

19. The active matrix substrate as set forth in claim 1, wherein the retention capacitor lines include a first retention capacitor line group that is driven in response to a first retention capacitor line signal from the retention capacitor line driving circuit and a second retention capacitor line group that is driven in response to a second retention capacitor line signal from an external signal source.

20. The active matrix substrate as set forth in claim 19, wherein the second retention capacitor line signal is a common electrode potential.

21. The active matrix substrate as set forth in claim 1 wherein the signal from the external signal source is a common electrode potential.

22. A liquid crystal display device, comprising an active matrix substrate as set forth in claim 1,

the retention capacitor line driving circuit supplying the retention capacitor line signal to the retention capacitor lines which define retention capacitors with the pixel electrodes, so as to create display while pixel potentials written in the pixel electrodes from the data signal lines are changed in directions corresponding to polarities of the pixel potentials.

23. A television receiver, comprising a liquid crystal display device as set forth in claim 22 and a tuner section for receiving television broadcasting.

24. A liquid crystal panel, comprising an active matrix substrate as set forth in claim 1.