Three-dimensional memory structures having shared pillar memory cells

• US 9,076,518 B2
• Filed: 02/03/2012
• Issued: 07/07/2015
• Est. Priority Date: 12/24/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Harari, Eliyahou
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): ASSOUMAN, HERVE-LOUIS Y
• Application Number:
  US13/365,991
• Publication Number:
  US 20120135580A1
• Time in Patent Office: 1,250 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/34 Material includes an oxide or a nitride
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/52 Structure characterized by the electrode material, shape, etc.
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels
• CPC Class Codes: H10N 70/8845 : Carbon or carbides

Abstract

A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

Claims

1. A method of making non-volatile memory, comprising:

forming a first set of substantially parallel and substantially coplanar conductors;

forming a second set of substantially parallel and substantially coplanar conductors vertically separated from the first set of conductors; and

forming a set of pillars in communication with the first set of conductors and the second set of conductors, each pillar of the set of pillars having a first end surface and a second end surface, the first end surface contacting one conductor of the first set of conductors, the second end surface contacting two conductors of the second set of conductors, said each pillar including a first non-volatile storage element having a first state change element and a first steering element and a second non-volatile storage element having a second state change element and a second steering element.

2. A method according to claim 1, wherein:

forming the set of pillars includes forming a first pillar, the first end surface of the first pillar contacting a first conductor of the first set of conductors, the second end surface of the first pillar including a first portion contacting a second conductor of the second set of conductors and a second portion contacting a third conductor of the second set of conductors;

the first non-volatile storage element of the first pillar is addressable by the first conductor and the second conductor; and

the second non-volatile storage element of the first pillar is addressable by the first conductor and the third conductor.

3. A method according to claim 2, wherein:

the first steering element of the first pillar is a first diode, the first diode including a first electrode terminating at the first end surface and a second electrode separated from the first electrode by a first intrinsic region; and

the second steering element of the first pillar is a second diode, the second diode sharing the first electrode with the first diode and including a third electrode separated from the first electrode by the first intrinsic region.

4. A method according to claim 3, wherein:

the first set of conductors are elongated in a first direction with spaces therebetween in a second direction, the second direction being substantially perpendicular to the first direction;

the second set of conductors are elongated in the second direction with spaces therebetween in the first direction;

the second electrode is further separated from the first electrode by a second intrinsic region, the second intrinsic region having a length in the first direction that is less than a length of the first intrinsic region in the first direction; and

the third electrode is further separated from the first electrode by a third intrinsic region, the third intrinsic region having a length in the first direction that is less than a length of the first intrinsic region in the first direction, the second intrinsic region and the third intrinsic region being separated in the first direction by a dielectric region.

5. A method according to claim 3, wherein:

the first state change element contacts the second electrode and terminates at the first portion of the second end surface; and

the second state change element contacts the third electrode and terminates at the second portion of the second end surface.

6. A method according to claim 3, wherein:

the second electrode terminates at the first portion of the second end surface;

the third electrode terminates at the second portion of the second end surface;

the first state change element contacts the second intrinsic region and the second electrode; and

the second state change element contacts the third intrinsic region and the third electrode.

7. A method of making non-volatile memory, comprising:

forming a first set of conductors;

forming a second set of conductors vertically separated from the first set of conductors; and

forming a set of pillars in communication with the first set of conductors and the second set of conductors, each pillar of the set of pillars having a first end surface and a second end surface, the first end surface contacting one conductor of the first set of conductors, the second end surface contacting two conductors of the second set of conductors, said each pillar including a first non-volatile storage element having a first state change element and a first steering element and a second non-volatile storage element having a second state change element and a second steering element.

8. A method according to claim 7, wherein:

forming a first set of conductors comprises forming a first set of parallel and coplanar conductors; and

forming a second set of conductors comprises forming a second set of parallel and coplanar conductors.

9. A method according to claim 8, wherein:

the first set of conductors is formed at a first distance above a substrate; and

the second set of conductors is formed at a second distance above a substrate.

10. A method according to claim 9, wherein:

forming the set of pillars includes forming a first pillar, the first end surface of the first pillar contacting a first conductor of the first set of conductors, the second end surface of the first pillar including a first portion that contacts a second conductor of the second set of conductors and a second portion that contacts a third conductor of the second set of conductors;

the first non-volatile storage element of the first pillar is addressable by the first conductor and the second conductor; and

the second non-volatile storage element of the first pillar is addressable by the first conductor and the third conductor.

11. A method according to claim 10, wherein:

the first steering element of the first pillar is a first diode, the first diode including a first electrode terminating at the first end surface and a second electrode separated from the first electrode by a first intrinsic region; and

the second steering element of the first pillar is a second diode, the second diode sharing the first electrode with the first diode and including a third electrode separated from the first electrode by the first intrinsic region.

12. A method according to claim 11, wherein:

the first set of conductors are elongated in a first direction with spaces therebetween in a second direction, the second direction being perpendicular to the first direction;

the second set of conductors are elongated in the second direction with spaces therebetween in the first direction;

the second electrode is further separated from the first electrode by a second intrinsic region, the second intrinsic region having a length in the first direction that is less than a length of the first intrinsic region in the first direction; and

the third electrode is further separated from the first electrode by a third intrinsic region, the third intrinsic region having a length in the first direction that is less than a length of the first intrinsic region in the first direction, the second intrinsic region and the third intrinsic region being separated in the first direction by a dielectric region.

13. A method according to claim 11, wherein:

the first state change element contacts the second electrode and terminates at the first portion of the second end surface; and

the second state change element contacts the third electrode and terminates at the second portion of the second end surface.

14. A method according to claim 11, wherein:

the second electrode terminates at the first portion of the second end surface;

the third electrode terminates at the second portion of the second end surface;

the first state change element contacts the second intrinsic region and the second electrode; and

the second state change element contacts the third intrinsic region and the third electrode.

15. A method of making non-volatile memory, comprising:

forming a first conductor;

forming a second conductor and a third conductor that are coplanar and vertically separated from the first conductor; and

forming a set of pillars in communication with the first conductor, the second conductor, and the third conductor, each pillar of the set of pillars having a first end surface and a second end surface, the first end surface contacts the first conductor, the second end surface includes a first portion that contacts the second conductor and a second portion that contacts the third conductor, said each pillar including a first non-volatile storage element having a first state change element and a first steering element and a second non-volatile storage element having a second state change element and a second steering element.

16. A method according to claim 15, wherein:

forming the set of pillars includes forming a first pillar;

the first non-volatile storage element of the first pillar is addressable by the first conductor and the second conductor; and

the second non-volatile storage element of the first pillar is addressable by the first conductor and the third conductor.

17. A method according to claim 16, wherein:

the first steering element of the first pillar is a first diode, the first diode including a first electrode terminating at the first end surface and a second electrode separated from the first electrode by a first intrinsic region; and

the second steering element of the first pillar is a second diode, the second diode sharing the first electrode with the first diode and including a third electrode separated from the first electrode by the first intrinsic region.

18. A method according to claim 16, wherein:

the first set of conductors are elongated in a first direction with spaces therebetween in a second direction, the second direction being perpendicular to the first direction;

the second set of conductors are elongated in the second direction with spaces therebetween in the first direction;

the second electrode is further separated from the first electrode by a second intrinsic region, the second intrinsic region having a length in the first direction that is less than a length of the first intrinsic region in the first direction; and

the third electrode is further separated from the first electrode by a third intrinsic region, the third intrinsic region having a length in the first direction that is less than a length of the first intrinsic region in the first direction, the second intrinsic region and the third intrinsic region being separated in the first direction by a dielectric region.

19. A method according to claim 17, wherein:

the first state change element contacts the second electrode and terminates at the first portion of the second end surface; and

the second state change element contacts the third electrode and terminates at the second portion of the second end surface.

20. A method according to claim 17, wherein:

the second electrode terminates at the first portion of the second end surface;

the third electrode terminates at the second portion of the second end surface;

the first state change element contacts the second intrinsic region and the second electrode; and

the second state change element contacts the third intrinsic region and the third electrode.