Non-volatile write buffer data retention pending scheduled verification
First Claim
Patent Images
1. A method comprising:
- storing input write data in a non-volatile (NV) buffer, the input write data having an associated logical address;
transferring a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer;
initiating a count to denote a predetermined elapsed time interval; and
performing a verify operation at responsive to the conclusion of the predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory.
1 Assignment
0 Petitions
Accused Products
Abstract
Method and apparatus for managing data in a memory. In accordance with some embodiments, a non-volatile (NV) buffer is adapted to store input write data having a selected logical address. A write circuit is adapted to transfer a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer. A verify circuit is adapted to perform a verify operation at the conclusion of a predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory. The input write data are retained in the NV buffer until successful transfer is verified.
-
Citations
25 Claims
-
1. A method comprising:
-
storing input write data in a non-volatile (NV) buffer, the input write data having an associated logical address; transferring a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer; initiating a count to denote a predetermined elapsed time interval; and performing a verify operation at responsive to the conclusion of the predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. An apparatus comprising:
-
a non-volatile (NV) buffer adapted to store input write data having a selected logical address; a write circuit adapted to transfer a copy of the input write data to an NV main memory while retaining the stored input write data in the NV buffer; a timer circuit adapted to initiate a count to denote a predetermined elapsed time interval responsive to the transfer of the copy of the input write data to the NV main memory; and a verify circuit adapted to perform a verify operation at the conclusion of the predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
-
-
25. An apparatus comprising:
-
a non-volatile (NV) buffer comprising a plurality of rewriteable non-volatile memory cells arranged as a content addressable memory (CAM) and adapted to store input write data having a selected logical address; an NV main memory comprising a plurality of eraseable flash memory cells; a write circuit adapted to transfer a copy of the input write data to the NV main memory while retaining the stored input write data in the NV buffer; a timer circuit adapted to initiate demarking a predetermined elapsed time interval; and a verify circuit which, responsive to receipt during the predetermined elapsed time interval of updated write data having the selected logical address, instructs the timer circuit to discontinue demarking of the predetermined elapsed time interval and reinitializes the timer circuit to commence demarking a second predetermined elapsed time interval for the updated write data, and wherein the verify circuit, responsive to an absence during the predetermined elapsed time interval of updated write data having the selected logical address, performs a verify operation at the conclusion of the predetermined elapsed time interval to verify successful transfer of the copy of the input write data to the NV main memory.
-
Specification