Memory devices and method of fabricating same

• US 9,076,681 B2
• Filed: 09/27/2013
• Issued: 07/07/2015
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Chang-Ming, Liu, Shih-Chang, Tsai, Chia-Shiung
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US14/039,925
• Publication Number:
  US 20150091071A1
• Time in Patent Office: 648 Days
• Field of Search: 438/267, 438/596
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate electrode is an L-shaped structure, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Claims

1. A method comprising:

forming a control gate structure over a substrate;

depositing a charge storage layer over the control gate structure;

depositing a memory gate layer over the charge storage layer, wherein the memory gate layer conforms to the charge storage layer;

depositing a first dielectric layer over the memory gate layer;

applying a first etching process to the first dielectric layer and the memory gate layer to form a first memory gate structure, wherein;

the first memory gate structure is formed along a sidewall of the control gate structure; and

a remaining portion of the memory gate layer is an L-shaped structure;

forming a first spacer along a sidewall of the first memory gate structure;

applying a second etching process to the charge storage layer to form an L-shaped charge storage layer, wherein the L-shaped charge storage layer is located between the first memory gate structure and the control gate structure;

recessing an upper portion of the memory gate structure; and

forming a second spacer over the memory gate structure.

2. The method of claim 1, further comprising:

forming a first drain/source region adjacent to the memory gate structure and a second drain/source region adjacent to the control gate structure;

forming a first salicide region over the first drain/source region; and

forming a second salicide region over the second drain/source region.

3. The method of claim 1, further comprising:

depositing a gate dielectric layer over the substrate;

depositing a control gate electrode layer over the gate dielectric layer;

depositing a first hard mask layer over the control gate electrode layer;

depositing a second hard mask layer over the first hard mask layer; and

forming the control gate structure through a patterning process.

4. The method of claim 1, further comprising:

forming a first oxide layer over the substrate and the control gate structure;

forming the charge storage layer over the first oxide layer, wherein the charge storage layer is a silicon dot layer; and

forming a second oxide layer over the charge storage layer.

5. The method of claim 1, wherein:

the first gate structure comprises an L-shaped memory gate electrode layer.

6. The method of claim 5, wherein:

the L-shaped memory gate electrode layer is covered by spacers and oxide.

7. The method of claim 1, further comprising:

forming a contact etch stop layer (CESL) over the memory gate structure and the control gate structure;

depositing an inter-layer dielectric layer over the contact etch stop layer, wherein the memory gate structure and the control gate structure are embedded in the inter-layer dielectric layer;

performing a chemical mechanical polishing process on the inter-layer dielectric layer until a top surface of the control gate is exposed; and

forming contact plugs coupled to a first drain/source region and a second drain/source region.

8. A method comprising:

forming a control gate structure over a substrate;

forming an Oxide-Silicon-Oxide layer over the control gate structure;

depositing a memory gate layer over the Oxide-Silicon-Oxide layer, wherein the memory gate layer is a conformal film;

depositing a memory gate spacer layer over the memory gate layer;

forming a first memory gate structure through a first etching process, wherein the first memory gate structure is formed along a sidewall of the control gate structure;

forming a first spacer along a sidewall of the first memory gate structure;

applying a second etching process to a top oxide layer of the Oxide-Silicon-Oxide layer;

applying a third etching process to a silicon dot layer of the Oxide-Silicon-Oxide layer and the memory gate layer of the first memory gate structure;

forming a second spacer over the memory gate structure; and

forming a first drain/source region adjacent to the memory gate structure and a second drain/source region adjacent to the control gate structure.

9. The method of claim 8, further comprising:

forming a bottom oxide layer over the substrate and the control gate structure;

forming the silicon dot layer over the bottom oxide layer; and

forming the top oxide layer over the silicon dot layer.

10. The method of claim 9, wherein:

the bottom oxide layer is of a thickness of about 50 angstrom;

the silicon dot layer is of a thickness of about 100 angstrom; and

the top oxide layer is of a thickness of about 100 angstrom.

11. The method of claim 8, further comprising:

forming an opening adjacent to the memory gate structure;

filling a plurality of conductive materials into the opening to from a conductive region, wherein the conductive region is electrically coupled to the memory gate structure; and

forming a contact plug over the conductive region, wherein the contact plug is electrically coupled to the conductive region.

12. The method of claim 8, wherein:

during the step of forming the first memory gate structure through the first etching process, critical dimensions of the memory gate structure is determined by a thickness of a sidewall portion of the memory gate spacer layer.

13. The method of claim 8, wherein:

an exposed portion of the silicon dot layer of the Oxide-Silicon-Oxide layer is removed by an isotropic dry etching process.

14. The method of claim 8, wherein:

the silicon dot layer is a charge storage layer.

15. A method comprising:

depositing a charge storage layer over a control gate structure, wherein the charge storage layer comprise a first oxide layer, a silicon dot layer and a second oxide layer;

depositing a memory gate layer over the charge storage layer;

depositing a nitride layer over the memory gate layer;

applying a first etching process to the nitride layer and the memory gate layer until a top surface of the second oxide layer is exposed, wherein a remaining portion of the memory gate layer is an L-shaped structure after performing the first etching process;

forming a thin spacer layer along a sidewall of a memory gate structure comprising the remaining portion of the memory gate layer;

applying a second etching process to the charge storage layer to form an L-shaped charge storage layer, wherein the L-shaped charge storage layer is located between the memory gate structure and the control gate structure;

recessing an upper portion of the memory gate structure; and

forming a top spacer layer over the memory gate structure.

16. The method of claim 15, further comprising:

depositing the memory gate layer over the charge storage layer, wherein the memory gate layer conforms to the charge storage layer.

17. The method of claim 15, further comprising:

removing the top spacer layer over drain/source regions through a third etching process applied to the top spacer layer, wherein a top surface of the memory gate structure is protected by a remaining portion of the top spacer layer after performing the third etching process.

18. The method of claim 15, further comprising:

depositing the first oxide layer over the control gate structure;

depositing the silicon dot layer over the first oxide layer; and

depositing the second oxide layer over the silicon dot layer.

19. The method of claim 15, further comprising:

forming a first drain/source region and a second drain/source region through an ion implantation process, wherein the first drain/source region and the second drain/source region are on opposite sides of the control gate structure.

20. The method of claim 19, further comprising:

depositing a contact etch stop layer over the memory gate structure and the control gate structure;

depositing an inter-layer dielectric layer, wherein the memory gate structure and the control gate structure are embedded in the inter-layer dielectric layer;

performing a chemical mechanical polishing process on the inter-layer dielectric layer until a top surface of the control gate structure is exposed; and

forming contact plugs coupled to a first drain/source region and a second drain/source region.