Memory devices and method of fabricating same
First Claim
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1. A method comprising:
- forming a control gate structure over a substrate;
depositing a charge storage layer over the control gate structure;
depositing a memory gate layer over the charge storage layer, wherein the memory gate layer conforms to the charge storage layer;
depositing a first dielectric layer over the memory gate layer;
applying a first etching process to the first dielectric layer and the memory gate layer to form a first memory gate structure, wherein;
the first memory gate structure is formed along a sidewall of the control gate structure; and
a remaining portion of the memory gate layer is an L-shaped structure;
forming a first spacer along a sidewall of the first memory gate structure;
applying a second etching process to the charge storage layer to form an L-shaped charge storage layer, wherein the L-shaped charge storage layer is located between the first memory gate structure and the control gate structure;
recessing an upper portion of the memory gate structure; and
forming a second spacer over the memory gate structure.
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Abstract
A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate electrode is an L-shaped structure, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
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Citations
20 Claims
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1. A method comprising:
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forming a control gate structure over a substrate; depositing a charge storage layer over the control gate structure; depositing a memory gate layer over the charge storage layer, wherein the memory gate layer conforms to the charge storage layer; depositing a first dielectric layer over the memory gate layer; applying a first etching process to the first dielectric layer and the memory gate layer to form a first memory gate structure, wherein; the first memory gate structure is formed along a sidewall of the control gate structure; and a remaining portion of the memory gate layer is an L-shaped structure; forming a first spacer along a sidewall of the first memory gate structure; applying a second etching process to the charge storage layer to form an L-shaped charge storage layer, wherein the L-shaped charge storage layer is located between the first memory gate structure and the control gate structure; recessing an upper portion of the memory gate structure; and forming a second spacer over the memory gate structure. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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forming a control gate structure over a substrate; forming an Oxide-Silicon-Oxide layer over the control gate structure; depositing a memory gate layer over the Oxide-Silicon-Oxide layer, wherein the memory gate layer is a conformal film; depositing a memory gate spacer layer over the memory gate layer; forming a first memory gate structure through a first etching process, wherein the first memory gate structure is formed along a sidewall of the control gate structure; forming a first spacer along a sidewall of the first memory gate structure; applying a second etching process to a top oxide layer of the Oxide-Silicon-Oxide layer; applying a third etching process to a silicon dot layer of the Oxide-Silicon-Oxide layer and the memory gate layer of the first memory gate structure; forming a second spacer over the memory gate structure; and forming a first drain/source region adjacent to the memory gate structure and a second drain/source region adjacent to the control gate structure. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method comprising:
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depositing a charge storage layer over a control gate structure, wherein the charge storage layer comprise a first oxide layer, a silicon dot layer and a second oxide layer; depositing a memory gate layer over the charge storage layer; depositing a nitride layer over the memory gate layer; applying a first etching process to the nitride layer and the memory gate layer until a top surface of the second oxide layer is exposed, wherein a remaining portion of the memory gate layer is an L-shaped structure after performing the first etching process; forming a thin spacer layer along a sidewall of a memory gate structure comprising the remaining portion of the memory gate layer; applying a second etching process to the charge storage layer to form an L-shaped charge storage layer, wherein the L-shaped charge storage layer is located between the memory gate structure and the control gate structure; recessing an upper portion of the memory gate structure; and forming a top spacer layer over the memory gate structure. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification