Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

• US 9,076,761 B2
• Filed: 05/31/2012
• Issued: 07/07/2015
• Est. Priority Date: 06/14/2011
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Watanabe, Tomokatsu, Miura, Naruhisa, Furuhashi, Masayuki, Hino, Shiro, Tanioka, Toshikazu
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US14/116,259
• Publication Number:
  US 20140061675A1
• Time in Patent Office: 1,132 Days
• Field of Search: 257/288, 257/328, 257/329, 257/E29.027, 257/E29.066, 257/E29.197, 257/E29.198
• US Class Current: 1/1
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A silicon carbide semiconductor device that is able to increase the gate reliability, and to provide a method for manufacturing the silicon carbide semiconductor device, and that includes: a source electrode selectively formed on a source region; a gate insulating film formed so as to extend over the source region; and a gate electrode formed on the gate insulating film. The source region includes a first source region located below the source electrode, and a second source region surrounding the first source region. The doping concentration in a superficial layer of the second source region is lower than the doping concentration in a superficial layer of the first source region. The doping concentration in the second source region is higher in a deep portion than in a superficial portion thereof.

Claims

1. A silicon carbide semiconductor device comprising:

a drift layer having a first conductivity type and made of silicon carbide;

a base region having a second conductivity type and selectively formed in a superficial layer of said drift layer;

a source region having the first conductivity type and selectively formed in a superficial layer of said base region;

a source electrode selectively formed on said source region;

a gate insulating film formed so as to extend over said drift layer, said base region, and an area of said source region where said source electrode is not formed; and

a gate electrode formed on said gate insulating film,

said source region including a first source region and a second source region, said first source region being arranged below said source electrode, said second source region being arranged below said gate electrode and formed so as to surround said first source region in a plan view,

a doping concentration in a superficial layer of said second source region being lower than a doping concentration in a superficial layer of said first source region,

a doping concentration in said second source region being higher in a deep portion than in a superficial portion thereof.

2. The silicon carbide semiconductor device according to claim 1, wherein

the doping concentration in a region of said second source region ranging from the superficial layer to the 100 nm depth is lower than the doping concentration in the superficial layer of said first source region.

3. The silicon carbide semiconductor device according to claim 1, wherein

the doping concentration in a region of said second source region ranging from the superficial layer to the 100 nm depth is 1×

10¹⁶ to 1×

10¹⁸ cm<sup>−

3</sup>.

4. The silicon carbide semiconductor device according to claim 1, wherein

the doping concentration in the superficial layer of said first source region is 1×

10¹⁹ to 1×

10²¹ cm<sup>−

3</sup>.

5. The silicon carbide semiconductor device according to claim 1, wherein

the relationship of 4d_OX/3<

d_X<

d_GS+d_pcon/2−

0.5×

(ρ

cS/RN+d_pcon²)^1/2 is satisfied, where;

an end portion of said gate electrode at said source electrode side is defined as the origin of the horizontal coordinate axis;

d_X represents the distance from said origin to said second source region;

d_GS represents the distance from said origin to the center of said source electrode;

d_ncon represents the horizontal width of said first source region;

d_OX represents the vertical thickness of said gate insulating film;

d_ncon² represents the area of said first source region;

N represents the number of cells included in an element;

S represents the area of an active region of the element;

ρ

c represents the ohmic contact resistivity;

R represents the on-resistivity of the element; and

d_pcon represents the horizontal width of a contact region having the second conductivity type and formed within said first source region, said contact region having a higher impurity concentration than the impurity concentration in said base region.

6. A silicon carbide semiconductor device comprising:

a drift layer having a first conductivity type and made of silicon carbide;

a base region having a second conductivity type and selectively formed in a superficial layer of said drift layer;

a source region selectively formed in a superficial layer of said base region;

a source electrode selectively formed on said source region;

a gate insulating film formed so as to extend over said drift layer, said base region, and an area of said source region where said source electrode is not formed; and

a gate electrode formed on said gate insulating film,

said source region including an upper-layer region and a lower-layer region, said upper-layer region having the second conductivity type and formed in a superficial portion, said lower-layer region having the first conductivity type and formed in a lower layer below said upper-layer region,

said source electrode having a lower end thereof buried in said source region so as to reach said lower-layer region,

said upper-layer region of said source region being formed directly on said lower-layer region of said source region.

7. The silicon carbide semiconductor device according to claim 6, wherein

the boundary between said upper-layer region and said lower-layer region is located at a depth of 5 to 100 nm from a superficial layer of said upper-layer region.

8. The silicon carbide semiconductor device according to claim 6, wherein

an entire width of said upper-layer region of said source region is formed on said lower-layer region of said source region.

9. The silicon carbide semiconductor device according to claim 6, wherein

an edge of said upper-layer region of said source region which is furthest away from said source electrode is vertically aligned with an edge of said lower-layer region of said source region which is furthest away from said source electrode.