Anchoring structure and intermeshing structure

• US 9,076,821 B2
• Filed: 02/22/2012
• Issued: 07/07/2015
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Vogl, Erwin, Zundel, Markus
• Primary Examiner(s): Feeney, Brett
• Assistant Examiner(s): Hillman, Damian A
• Application Number:
  US13/402,394
• Publication Number:
  US 20120211891A1
• Time in Patent Office: 1,231 Days
• Field of Search: 257/773
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13599 Material
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29599 Material
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure.

Claims

1. An anchoring structure for a metal structure of a semiconductor device, the anchoring structure comprising:

an anchoring recess structure comprising at least one overhanging sidewall, wherein the metal structure is at least partly arranged within the anchoring recess structure and below an overhang of the overhanging sidewall, wherein the overhanging sidewall is formed by a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate comprises mono-crystalline semiconductor in which the anchoring recess structure is formed so that the overhanging sidewall is formed by the semiconductor.

2. The anchoring structure according to claim 1, wherein the anchoring recess structure is partially filled with polysilicon.

3. The anchoring structure according to claim 1, wherein the overhanging sidewall has an angle of at least −

3°

related to a normal direction perpendicular to a main surface of the semiconductor device.

4. The anchoring structure according to claim 1, wherein the metal structure comprises deposited conforming metal such that the metal structure is anchored by the anchoring recess structure and abuts the overhanging sidewall.

5. The anchoring structure according to claim 1, wherein the metal structure is arranged such that the metal structure is adapted to the semiconductor substrate by an undercut tight fit.

6. An intermeshing structure for a device comprising a cell field and formed on a substrate, the intermeshing structure comprising:

an intermediate insulating layer which is structured such that the intermediate insulating layer is interrupted by at least one contact hole;

a metal structure on the intermediate insulating layer for connecting the cell field; and

a support structure comprising polysilicon and embedded in a recess formed in the substrate and aligned with the contact hole, wherein the support structure is not part of the cell field,

wherein the metal structure extends through the contact hole up to the support structure to which the metal structure is adherently connected.

7. The intermeshing structure according to claim 6, wherein the intermediate insulating layer is structured such that the intermediate insulating layer is interrupted by a plurality of contact holes,

and wherein a plurality of support structures not being part of the cell field is embedded in a plurality of recesses formed in the substrate and aligned with a respective contact hole, and

wherein the metal structure extends through the plurality of contact holes up to the plurality of support structures to which the metal structure is adherently connected.

8. The intermeshing structure according to claim 6, wherein the recess is formed by a trench in which the support structure is embedded, wherein the trench is aligned with the contact hole.

9. The intermeshing structure according to claim 6, wherein the recess is coated by an insulating layer so as to insulate the support structure against the substrate.

10. The intermeshing structure according to claim 6, wherein the recess is arranged within a peripheral area of the device, wherein the peripheral area surrounds the cell field.

11. The intermeshing structure according to claim 10, wherein the peripheral area comprises a gate-runner structure and/or a contact region.

12. The intermeshing structure according to claim 10, wherein the peripheral area is separated from the cell field by a channel stop trench.

13. The intermeshing structure according to claim 12, wherein the channel stop is formed by a trench which extends from a main surface of the substrate at least partially into the substrate, wherein at least one electrode is arranged in the channel stop trench.

14. The intermeshing structure according to claim 6, wherein the metal structure comprises titanium and azote and/or titanium-titanium-azote-tungsten-aluminum-copper.

16. The intermeshing structure according to claim 6, wherein the support structure is not part of a transistor.

17. The intermeshing structure according to claim 6, wherein the intermediate insulating layer comprises oxide.

15. An intermeshing structure for a device comprising a cell field and formed on a substrate, the intermeshing structure comprising:

an intermediate insulating layer which is structured such that the intermediate insulating layer is interrupted by at least one contact hole;

a metal structure on the intermediate insulating layer for connecting the cell field; and

a support structure comprising polysilicon and embedded in a recess formed in the substrate and aligned with the contact hole, wherein the support structure is not part of the cell field,

wherein the metal structure extends through the contact hole up to the support structure to which the metal structure is adherently connected,

wherein the recess is coated by an insulating layer so as to insulate the support structure against the substrate,

wherein the cell field is composed of at least one vertical transistor structure or at least one lateral transistor structure, and

wherein the support structure is connected to the at least one vertical transistor structure or to the at least one lateral transistor merely via the metal structure.

18. An intermeshing structure comprising:

a substrate comprising a main surface and a mono-crystalline semiconductor abutting the main surface of the substrate;

a recess formed in the mono-crystalline semiconductor within the main surface of the substrate;

an insulating layer formed on the main surface of the substrate; and

a conductor layer structure comprising

a metal layer which is formed on the insulating layer and extends through a hole of the insulating layer into the recess, and

polysilicon at a bottom of the recess, wherein the polysilicon abuts the metal layer.

19. A semiconductor device comprising:

a substrate;

an active area formed in the substrate;

an insulating layer formed on a surface of the substrate; and

a metal layer formed on the insulating layer and contacting the active area, wherein a recess is formed in the substrate and filled with polysilicon, and

wherein the metal layer extends through a hole in the insulating layer and adheres to the polysilicon.