Insulated gate bipolar transistor with mesa sections between cell trench structures and method of manufacturing

• US 9,076,838 B2
• Filed: 09/13/2013
• Issued: 07/07/2015
• Est. Priority Date: 09/13/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Laven, Johannes Georg, Philippou, Alexander, Schulze, Hans-Joachim, Jaeger, Christian, Baburske, Roman, Vellei, Antonio
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): IVANOV, PAVEL G
• Application Number:
  US14/026,383
• Publication Number:
  US 20150076554A1
• Time in Patent Office: 662 Days
• Field of Search: 257/330, 257/341, 257/E29.201, 257/E29.262
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

An IGBT includes a mesa section that extends between two cell trench structures from a first surface of a semiconductor portion to a layer section of the semiconductor portion. A source region, which is electrically connected to an emitter electrode, is formed in the mesa section. A doped region, which is separated from the source region by a body region of a complementary conductivity type, includes a first portion with a first mean net impurity concentration and a second portion with a second mean net impurity concentration exceeding at least ten times the first mean net impurity concentration. In the mesa section the first portion extends from the body region to the layer section. The second portions of the doped region virtually narrow the mesa sections in a normal on-state of the IGBT.

Claims

1. An insulated gate bipolar transistor, comprising:

a mesa section extending, between two cell trench structures, from a first surface of a semiconductor portion to a layer section of the semiconductor portion;

a source region formed in the mesa section and electrically connected to an emitter electrode; and

a doped region separated from the source region by a body region of a complementary conductivity type, the doped region comprising a first portion with a first mean net impurity concentration and a second portion with a second mean net impurity concentration exceeding at least ten times the first mean net impurity concentration,

wherein the first portion extends from the body region to the layer section,

wherein the first portion is interposed between the second portion and one of the two cell trench structures.

2. The insulated gate bipolar transistor according to claim 1, wherein

the second mean net impurity concentration exceeds at least ten times a third mean net impurity concentration in a directly adjoining portion of a drift layer in the layer section.

3. The insulated gate bipolar transistor according to claim 1, wherein

a third mean net impurity concentration in a portion of the drift layer directly adjoining the first portion and the first mean net impurity concentration deviate from each other by not more than 10%.

4. The insulated gate bipolar transistor according to claim 1, wherein

the second portion of the doped region directly adjoins the body region.

5. The insulated gate bipolar transistor according to claim 1, wherein

the second portion of the doped region is spaced from the layer section.

6. The insulated gate bipolar transistor according to claim 1, further comprising:

a gate electrode in a first one of the two cell trench structures and a field electrode in a second one of the two cell trench structures, wherein

the second portion directly adjoins the second cell trench structure and the first portion separates the second portion from the first cell trench structure.

7. The insulated gate bipolar transistor according to claim 1, wherein

the source region directly adjoins a first one of the two cell trench structures and the body region separates the source region from a second one of the two cell trench structures.

8. The insulated gate bipolar transistor according to claim 7, wherein

the second portion directly adjoins the second cell trench structure and the first portion separates the second portion from the first cell trench structure.

9. The insulated gate bipolar transistor according to claim 1, wherein

the second portion of the doped region is spaced from the body region.

10. The insulated gate bipolar transistor according to claim 1, wherein

the second portion extends over at most 50% of the vertical extension of the doped region.

11. The insulated gate bipolar transistor according to claim 1, wherein

the second portion extends over at least 50% of the lateral mesa width of the mesa section.

12. The insulated gate bipolar transistor according to claim 1, wherein

the second portion comprises two spatially separated sub-portions and the first portion separates the two sub-portions of the second portion.

13. The insulated gate bipolar transistor according to claim 1, wherein

first ones of the cell trench structures comprise gate electrodes and second ones of the cell trench structures comprise field electrodes,

the mesa section is formed between one of the first cell trench structures and one of the second cell trench structures,

the source region directly adjoins the first cell trench structure adjoining the mesa section,

the body region separates the source region from the second cell trench structure, and

the second portion of the doped region directly adjoins the second cell trench structure.

14. The insulated gate bipolar transistor according to claim 13, wherein

ancillary mesa sections are formed between pairs of the second cell trench structures, the ancillary mesa sections comprising secondary doped regions and secondary body regions separating the secondary doped portions from the first surface, the secondary doped portions comprising a first portion with the first mean net impurity concentration and a second portion with the second mean net impurity concentration, the first portion extending between the secondary body region and a drift layer in the layer section.

15. The insulated gate bipolar transistor according to claim 1, wherein

the second portions of the doped region contain sulphur S and/or selenium Se atoms.