Silicided recessed silicon

• US 9,076,888 B2
• Filed: 12/21/2006
• Issued: 07/07/2015
• Est. Priority Date: 09/01/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nejad, Hasan, Figura, Thomas A., Haller, Gordon A., Iyer, Ravi, Meldrim, John Mark, Harnish, Justin
• Primary Examiner(s): STARK, JARRETT J
• Application Number:
  US11/614,802
• Publication Number:
  US 20070105357A1
• Time in Patent Office: 3,120 Days
• Field of Search: 438/580, 438/581, 438/582, 438/583
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823443 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

Claims

1. A memory device comprising a pair of recessed access devices in a memory array, comprising:

a pair of trenches within semiconductive material of a semiconductor substrate, the trenches being separated from each other by a distance of from 30 nm to 50 nm;

a transistor gate dielectric layer lining the trenches, the lining forming a narrowed trench area within the each of the trenches;

a lower portion of the narrowed trench area filled with a single material consisting of a single conductive metal silicide transistor gate material containing at least two metals selected from the group consisting of tungsten, titanium, ruthenium, cobalt, nickel and tantalum, the metal silicide in direct physical contact with the dielectric layer lining a base of the trench and having an elevationally outermost surface that is elevationally recessed relative to the elevationally outermost surface of the semiconductive material within which the trench is received leaving a remaining volume in an upper portion of the narrowed trench area, the conductive metal silicide transistor gate material filling greater than 50% of the trench height;

individual channel regions extending across the trench beneath each of the trenches and extending along sidewalls of each trench; and

an insulative material received within the upper portion of the narrowed trench area elevationally over and in physical contact with the metal silicide across the elevationally outermost surface of the metal silicide and filling the remaining volume of the narrowed trench area.

2. The memory device of claim 1, wherein the at least two metals have opposite diffusivities relative to silicon.

3. The memory device of claim 1, wherein the metal silicide comprises a first metal selected from the group consisting of nickel, platinum and copper, and a second metal selected from the group consisting of cobalt, titanium and tantalum.

4. The memory device of claim 1, wherein one of the recessed access devices shares a source with an adjacent recessed access device.

5. The memory device of claim 1, wherein each of the trenches defines an opening having a width between 25 nm and 75 nm.

6. The memory device of claim 1, wherein 70-90 at. % of metal in the metal silicide comprises nickel.

7. The memory device of claim 6, wherein 10-30 at. % of metal in the metal silicide comprises cobalt.

15. The memory device of claim 1 wherein the transistor gate dielectric layer and the insulative material are different in composition.

8. A pair of recessed access devices, comprising:

a pair of trenches within semiconductive material of a semiconductor substrate, the semiconductive material having an elevationally outermost surface;

a transistor gate dielectric layer lining the trenches and received against the semiconductive material, the lining forming a narrowed trench area within each trench, the gate dielectric layer being received over and against the semiconductive material laterally outward of the trench;

a conductive metal silicide transistor gate material having at least two metals, a lower portion of the narrowed trench area being filled with a single material consisting of the metal silicide, the metal silicide contacting the dielectric layer along a base of the trench and having an elevationally outermost surface that is elevationally recessed relative to the elevationally outermost surface of the semiconductive material within which the trench is received leaving a remaining volume in an upper portion of the narrowed trench area, the metal silicide filling greater than 50% of the trench height;

an insulative material received within the upper portion of the narrowed trench area and filling the remaining volume of the narrowed trench area, the insulative material being in physical contact with the gate dielectric layer and in physical contact with the metal silicide across the elevationally outermost surface of the metal silicide, the gate dielectric layer having an elevationally outermost planar surface, the insulative material having an elevationally outermost planar surface which is coplanar with the elevationally outermost planar surface of the gate dielectric layer;

a channel region extending across the trench beneath each trench and extending along sidewalls of the trench; and

source/drain regions disposed an each side of each of the trenches, the source/drain regions protruding above the elevationally outermost surface of the semiconductive material.

9. The recessed access devices of claim 8, wherein the at least two metals have opposite diffusivities relative to silicon.

10. The recessed access devices of claim 8, wherein the metal silicide comprises a first metal selected from the group consisting of nickel, platinum and copper, and a second metal selected from the group consisting of cobalt, titanium and tantalum.

11. The recessed access devices of claim 8, wherein the recessed access devices shares a common source.

12. The recessed access devices of claim 8, wherein each trench defines an opening having a width between 25 nm and 75 nm.

13. The recessed access devices of claim 8, wherein 70-90 at. % of metal in the metal silicide comprises nickel.

14. The recessed access devices of claim 13, wherein 10-30 at. % of metal in the metal silicide comprises cobalt.

16. The recessed access devices of claim 8 wherein the transistor gate dielectric layer and the insulative material are different in composition.

17. A memory device comprising a pair of recessed access devices in a memory array, comprising;

a pair of trenches within semiconductive material of a semiconductor substrate, the semiconductive material having an elevationally outermost surface;

a transistor gate dielectric layer lining each trench and forming a narrowed trench area within the trench;

a lower portion of the narrowed trench area filled with a single material consisting of a single conductive metal silicide transistor gate material that fills at least 50% of the trench height leaving a remaining volume in an upper portion of the narrowed trench area, the metal silicide having an elevationally outermost surface that is elevationally recessed relative to the elevationally outermost surface of the semiconductive material within which the trench is received, the metal silicide comprising at least two metals; and

an insulative material received within the upper portion of the narrowed trench area elevationally over and in physical contact with the elevationally outermost surface of the metal silicide and filling the remaining volume of the narrowed trench area;

individual channel regions extending across the trench beneath each of the trenches that extend along sidewalls of the trenches; and

source/drain regions disposed an each side of each of the trenches, the source/drain regions protruding above the elevationally outermost surface of the semiconductive material.

18. A memory device comprising a pair of recessed access devices in a memory array, comprising:

a pair of trenches within semiconductive material of a semiconductor substrate, the semiconductive material having an elevationally outermost surface;

a transistor gate dielectric layer lining each trench and forming a narrowed trench area within the trench;

a lower portion of the narrowed trench area filled with a single material consisting of a single conductive metal silicide transistor gate material, the metal silicide having an elevationally outermost surface that is elevationally recessed relative to the elevationally outermost surface of the semiconductive material within which the trench is received leaving a remaining volume in an upper portion of the narrowed trench area, the metal silicide comprising at least two metals;

an insulative material received within the upper portion of the narrowed trench area and filling the remaining volume of the trench, the insulative material being of different composition from that of the transistor gate dielectric, the insulative material being elevationally over and in physical contact with the elevationally outermost surface of the metal silicide, the insulative material being received laterally against the gate dielectric layer;

a channel region extending across the trench beneath each trench and extending along sidewalls of the trench; and

source/drain regions disposed an each side of each of the trenches, the source/drain regions protruding above the elevationally outermost surface of the semiconductive material.