Method of forming a low power dissipation regulator and structure therefor

• US 9,077,256 B2
• Filed: 12/14/2010
• Issued: 07/07/2015
• Est. Priority Date: 12/14/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Basso, Christophe, Louvel, Jean-Paul
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Lee, Jye-June
• Application Number:
  US13/991,488
• Publication Number:
  US 20130272034A1
• Time in Patent Office: 1,666 Days
• Field of Search: 323/266, 323/274, 323/280, 323/281, 323/289, 363/21.04, 363/44, 363/65, 298/25
• US Class Current: 1/1
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: H02M 3/33546 with automatic control of the output voltage or current H02M3/33561 takes precedence
• CPC Class Codes: H05K 13/00 Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

In one embodiment, a method of forming a conditioning circuit includes configuring an output biasing network to provide a biasing voltage to an MOS transistor to enable the MOS transistor to operate in a saturated operating mode for input voltages that are less than a threshold voltage.

Claims

1. A method of forming a series pass regulator comprising:

configuring an input of the series pass regulator to receive an input voltage;

configuring the series pass regulator to form an output voltage on an output of the series pass regulator;

coupling a MOS transistor of the series pass regulator in series between the input and the output wherein the MOS transistor receives the input voltage from the input on a drain of the MOS transistor and conducts a current to the output from a source of the MOS transistor; and

configuring an output biasing network to form a gate-to-source voltage that is greater than a gate-to-source saturation voltage of the MOS transistor for conditions of the input voltage that are less than a threshold voltage of the series pass regulator.

2. The method of claim 1 further including configuring an input biasing network to form the gate-to-source voltage that is greater than a gate-to-source threshold voltage of the MOS transistor.

3. The method of claim 2 wherein configuring the input biasing network includes coupling a resistor between a gate of the MOS transistor and the input.

4. The method of claim 1 further including coupling a regulator element between a gate of the MOS transistor and a voltage return of the series pass regulator.

5. The method of claim 1 further including configuring the output to receive a voltage from a PWM regulator.

6. The method of claim 5 wherein coupling the MOS transistor of the series pass regulator in series between the input and the output includes configuring the MOS transistor for coupling between the input and an inductor of the PWM regulator.

7. The method of claim 1 wherein configuring the output biasing network includes coupling a zener diode between the output of the series pass regulator and the output biasing network, coupling a capacitor in parallel with the zener diode, and coupling energy from the capacitor to a gate of the MOS transistor.

8. A conditioning circuit for a power supply controller comprising:

a MOS transistor having a gate, a drain coupled to receive an input voltage, and a source coupled to form an output voltage;

a threshold detection circuit coupled to the gate of the MOS transistor, the threshold detection circuit having a threshold voltage; and

an output bias network coupled to the gate of the MOS transistor, the output bias network configured to receive the output voltage and provide a bias voltage to the gate of the MOS transistor for input voltages that are less than the threshold voltage.

9. The conditioning circuit of claim 8 further including an input biasing network configured to supply a bias voltage from the input voltage to the gate of the MOS transistor.

10. The conditioning circuit of claim 9 wherein the input biasing network forms a gate-to-source voltage that is greater than a gate-to-source threshold voltage of the MOS transistor.

11. The conditioning circuit of claim 9 further including a sense circuit configured to sense a Vds of the MOS transistor and inhibit the MOS transistor for Vds values that are greater than a first value.

12. The conditioning circuit of claim 8 wherein the threshold detection circuit includes a regulator circuit coupled to the gate of the MOS transistor.

13. The conditioning circuit of claim 8 wherein the output bias network receives a voltage from a switching power supply and forms a gate-to-source voltage for the MOS transistor.

14. The conditioning circuit of claim 13 wherein the output bias network is configured for coupling to a capacitor that is coupled to receive the voltage from the switching power supply and apply a voltage to the output bias network.

15. The conditioning circuit of claim 14 further including a zener diode having an anode coupled to receive the voltage from the switching power supply and a cathode coupled to the output bias network, and wherein the zener diode is coupled in parallel with the capacitor.

16. The conditioning circuit of claim 8 wherein the output bias network includes a resistor coupled to the gate of the MOS transistor.

17. A method of forming a conditioning circuit comprising:

coupling an MOS transistor in series between an input and an output of the conditioning circuit wherein the MOS transistor receives an input voltage from the input on a drain of the MOS transistor and forms an output voltage on a source of the MOS transistor;

configuring a threshold circuit with a threshold voltage and configuring the threshold circuit to cause the MOS transistor to operate in a linear operating mode for input voltages that are greater than the threshold voltage; and

configuring an output biasing network to provide a biasing voltage to the MOS transistor to enable the MOS transistor to operate in a saturated operating mode for input voltages that are less than the threshold voltage.

18. The method of claim 17 wherein configuring the output biasing network to provide the biasing voltage to the MOS transistor includes provide the biasing voltage to the MOS transistor under the condition of the output voltage being greater than the threshold voltage.

19. The method of claim 17 further including configuring the output of the conditioning circuit to receive a flyback voltage from an inductor of a PWM regulator.

20. The method of claim 17 further including coupling an input biasing network to provide a voltage to a gate of the MOS transistor that is less than the threshold voltage for values of the input voltage that are between zero and the threshold voltage under the condition of the output voltage being less than the input voltage.