Phase estimator

• US 9,077,361 B1
• Filed: 11/24/2014
• Issued: 07/07/2015
• Est. Priority Date: 12/24/2013
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Drago, Salvatore
• Primary Examiner(s): Nguyen, Khai M
• Application Number:
  US14/551,904
• Publication Number:
  US 20150180496A1
• Time in Patent Office: 225 Days
• Field of Search: 341/122, 341/155, 341/172
• US Class Current: 1/1
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter
• CPC Class Codes: H03M 1/462 Details of the control circuitry, e.g. of the successive approximation register
• CPC Class Codes: H03M 1/804 with charge redistribution
• CPC Class Codes: H04L 27/3818 using coherent demodulation, i.e. using one or more nominally phase synchronous carriers H04L27/227 and H04L27/389 take precedence

Abstract

A phase estimator comprising a first input terminal configured to receive a first analog input signal; a second input terminal configured to receive a second analog input signal, wherein the second analog input signal is 90° out of phase with the first analog input signal. The phase estimator is configured to provide a digital word representative of the phase of the first analog input signal and the second analog input signal. The phase estimator comprises a register configured to store N bits as a digital word a first reference signal generator, a second reference signal generator and a comparator.

Claims

1. A phase estimator comprising:

a first input terminal configured to receive a first analogue input signal;

a second input terminal configured to receive a second analogue input signal, wherein the second analogue input signal is 90°

out of phase with the first analogue input signal;

a register configured to store N bits as a digital word, where N is greater than one, the register comprising a register input terminal that is connectable to each of the bits in accordance with a pointer value, and a register output terminal configured to provide the digital word;

a first reference signal generator configured to receive the digital word from the register and the first analogue signal, and provide a first analogue reference signal as the product of the first analogue signal and sin(2π

*digital word);

a second reference signal generator configured to receive the digital word from the register and the second analogue signal, and provide a second analogue reference signal as the product of the second analogue signal and cos(2π

*digital word);

a comparator configured to compare the first analogue reference signal with the second analogue reference signal and provide to the input terminal of the register a binary feedback signal in accordance with the result of the comparison; and

wherein the output terminal of the register is configured to provide the digital word, wherein the digital word is representative of the phase of the first analogue input signal and the second analogue input signal.

2. The phase estimator of claim 1, wherein the phase estimator is configured to set the pointer value to the most significant bit in the digital word, set the digital word to a default word, and then repeatedly:

a) write the binary feedback signal to a bit in the register in accordance with the pointer value;

b) increment the pointer value;

c) for the bit in the register identified by the pointer value, set the bit as a default bit value;

d) provide a new first analogue reference signal and a new second analogue reference signal in accordance with the digital word stored in the register; and

e) compare the new first analogue reference signal with the new second analogue reference signal in order to provide to the input terminal of the register a binary feedback signal.

3. The phase estimator of claim 2, further configured to repeat steps a) to e) at a frequency equal to the product of a sampling frequency and N.

4. The phase estimator of claim 3, wherein the output terminal of the register is configured to update the digital word at a frequency equal to the inverse of a sampling period.

5. The phase estimator of claim 2, wherein the most significant bit of the default word is 1 and all other bits are zero, and wherein the default bit value is 1.

6. The phase estimator of claim 1, further comprising a first sample-and-hold component and a second sample-and-hold component, wherein:

the first sample-and-hold component has an input terminal that is connected to the first input terminal and an output terminal that is configured to provide a first time-discrete continuous-amplitude signal to the first reference signal generator; and

the second sample-and-hold component has an input terminal that is connected to the second input terminal and an output terminal that is configured to provide a second time-discrete continuous-amplitude signal to the second reference signal generator.

7. The phase estimator of claim 6, wherein the first sample-and-hold component and the second sample-and-hold component are configured to be clocked by a clock signal with a frequency equal to a sampling frequency.

8. The phase estimator of claim 1, wherein the first reference signal generator comprises a first digitally-controlled charge redistribution voltage divider configured to implement a sine function approximation, wherein the first digitally-controlled charge redistribution voltage divider comprises a first digitally controlled variable capacitor and a first fixed capacitor, the first digitally controlled variable capacitor is configured to provide a capacitance value of φ

C, where φ

is the digital word that is stored in the register and the first fixed capacitor has a fixed value of about 1.8C.

9. The phase estimator of claim 8, wherein the first digitally controlled variable capacitor comprises a first binary-weighted capacitor bank.

10. The phase estimator of claim 1, wherein the second reference signal generator comprises a second digitally-controlled charge redistribution voltage divider configured to implement a cosine function approximation, wherein the second digitally-controlled charge redistribution voltage divider comprises a second digitally controlled variable capacitor and a second fixed capacitor, the second digitally controlled variable capacitor is configured to provide a capacitance value of φ

C, where φ

is the inverse of the digital word that is stored in the register and the second fixed capacitor has a fixed value of about 1.8C.

11. The phase estimator of claim 1, wherein the first reference signal generator comprises a first digitally-controlled resistive voltage divider configured to implement a sine function approximation, wherein the first digitally-controlled resistor voltage divider comprises a first digitally controlled variable resistor and a first fixed resistor, the first digitally controlled variable resistor is configured to provide a resistor value of φ

R, where φ

is the digital word that is stored in the register and the first fixed resistor has a fixed value of about 1.8R.

12. The phase estimator of claim 11, wherein the first digitally controlled variable resistor comprises a first binary-weighted resistor array.

13. The phase estimator of claim 1, wherein the second reference signal generator comprises a second digitally-controlled resistive voltage divider configured to implement a cosine function approximation, wherein the second digitally-controlled resistive voltage divider comprises a second digitally controlled variable resistor and a second fixed resistor, wherein the second digitally controlled variable resistor is configured to provide a resistor value of φ

R, where φ

is the inverse of the digital word that is stored in the register and the second fixed resistor has a fixed value of about 1.8R.

14. An RF tuner comprising the phase estimator of claim 1.

15. An RPM sensor comprising the phase estimator of claim 1.