Multiple string digital to analog converter comprising a control circuit

• US 9,077,376 B2
• Filed: 03/14/2014
• Issued: 07/07/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Dempsey, Dennis A.
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US14/214,405
• Publication Number:
  US 20140285369A1
• Time in Patent Office: 480 Days
• Field of Search: 341/144, 341/118, 341/154, 341/153
• US Class Current: 1/1
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00
• CPC Class Codes: H03M 1/06 Continuously compensating for, or preventing, undesired influence of physical parameters periodically, e.g. by using stored correction values, H03M1/10
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/682 both converters being of the unary decoded type
• CPC Class Codes: H03M 1/765 using a single level of switches which are controlled by unary decoded digital signals

Abstract

A multi-string DAC is described and comprises at least two DAC stages. Each DAC stage comprises a string of impedance elements and a switching network. A control loop is provided to control the Ron of the switching network and provide code dependent control of switches in a DAC switching network.

Claims

1. A multistage digital to analog converter, DAC, comprising an output node and a plurality of DAC stages, at least one of the DAC stages comprising a string comprising a plurality of impedance elements coupled to a switching network comprising switches configured to provide at least one state change at the output node in response to a sensed change across the switching network, the DAC further comprising a control circuit coupled to the switching network and configured to provide code dependent compensation for, or control of, variances in the response of the switching network.

2. The DAC of claim 1 wherein the control circuit is responsive to changes in the input code to the DAC.

3. The DAC of claim 2 wherein the control circuit is coupled to a digital input of the DAC.

4. The DAC of claim 3 wherein the control circuit is configured to provide a variation in an output voltage of the control circuit in response to changes in an input code to the DAC.

5. The DAC of claim 4 wherein the switching network comprises switches of different switch type.

6. The DAC of claim 4 wherein the switching network comprises switches of the same switch type.

7. The DAC of claim 1 wherein the control circuit is coupled to a reference impedance.

8. The DAC of claim 7 wherein the control circuit is configured to provide compensation, or control, of, variances in response characteristics of one or more switches relative to the reference impedance.

9. The DAC of claim 8 wherein the control circuit is further configured to provide compensation for variances in the reference impedance.

10. The DAC of claim 8 wherein the reference impedance is matched to one or more impedance elements of an impedance string within the DAC.

11. The DAC of claim 1 wherein the control circuit is responsive to a control signal indicative of a change in the DAC code, the control circuit comprising a driver circuit providing a change in the gate level of a MOS device coupled to the switching network in response to a transition reflected by a change in the DAC code.

12. The DAC of claim 11 wherein control circuit comprises an operational amplifier.

13. The DAC of claim 1 wherein the control circuit comprises an operational amplifier providing a buffer and further comprises a boost element configured to compensate for delays in response characteristics of the operational amplifier to respond to changes in a DAC transition being effected using the switching network.

14. The DAC of claim 1 wherein at least one switch of the switching network comprises a MOS device and the control circuit is configured to vary voltages applied to a gate of the MOS device to provide compensation for, or control of, variances in the response of the switching network.

15. The DAC of claim 1 wherein at least one switch of the switching network comprises a MOS device and the control circuit is configured to vary voltages applied to a backgate of the MOS device to provide compensation for, or control of, variances in the response of the switching network.

16. The DAC of claim 1 comprising:

a first string with a plurality of impedance elements;

a second string with a plurality of impedance elements;

a first switching network adapted to couple a voltage produced across a at least one of the impedance elements in the first string across the second string in response to a digital input signal, said digital signal comprising a digital bit stream, the impedance elements in the second string configured to produce voltages in response to current passing from the first string through the first switching network to the second string to produce a corresponding analog signal to said digital input signal to an output node,

a second switching network comprising non-current carrying switches configured to provide at least one least significant bit, LSB, transition at the output node in response to a sensed change across the first switching network, and wherein the control circuit is coupled to the first switching network.

17. The DAC of claim 16 wherein switches of the first switch network are shared with the second string.

18. The DAC of claim 16 wherein the second string is configured to provide a loading effect across the first switching network and at least one resistor of the first resistor string.

19. The DAC of claim 1 wherein the control circuit is coupled to other switches of the DAC and is configured to provide code dependent compensation for, or control of, variances in the response of those switches.

20. A multistage digital to analog converter, DAC, comprising a plurality of DAC stages coupled via a switching network, the switching network comprising at least one MOS device, and further comprising switches configured to provide at least one state change in response to a sensed change across the switching network, the DAC further comprising a control circuit coupled to a gate terminal of the at least one MOS device and configured to vary voltages applied to the gate to provide compensation for, or control of, variances in the response of the switching network.

21. The DAC of claim 20 wherein the gate terminal is a back-gate terminal.

22. The DAC of claim 20 wherein the control circuit is configured to provide a code dependent compensation.

23. The DAC of claim 22 wherein the control circuit is coupled to a digital input of the DAC.

24. The DAC of claim 23 wherein the control circuit is configured to provide a relationship between an input code of the DAC and an output voltage of the control circuit that is used to provide the compensation.

25. The DAC of claim 20 wherein the control circuit provides compensation for, or control f, variances in the response characteristics of individual switches of the switching network.

26. The DAC of claim 25 wherein the control circuit is coupled to an analog input of the DAC.

27. The DAC of claim 20 wherein the control circuit is coupled to a node within the DAC and is responsive to changes in the operation of the DAC.

28. A method of converting a digital input signal to a corresponding analog output, the method comprising

Providing a digital bit stream to a digital to analog converter, DAC, the DAC comprising a plurality of DAC stages, at least one of the DAC stages comprising a string comprising a plurality of impedance elements coupled to a switching network,

Sensing a state change across the switching network, and

Providing a control circuit coupled to the switching network and

Detecting variances in the response of the switching network and in response to detection of said variances using the control circuit to provide code dependent compensation for, or control of, said variances.