Synchronous transfer of streaming data in a distributed antenna system
First Claim
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1. A method of generating a jitter reduced clock signal from signal transmitted over a communication medium, the method comprising:
- receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream;
generating a recovered clock signal that is phase locked to the binary encoded data stream with circuitry having a filter with a bandwidth that does not substantially block the long-term drift in the modulated signal; and
generating a jitter reduced clock signal by filtering the recovered clock signal using a filtering circuit having a bandwidth narrower than the bandwidth of the circuitry that is used for generating the recovered clock signal in order to remove jitter while allowing the jitter reduced clock signal to track drift of the binary encoded data stream.
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Abstract
Embodiments of the invention provide a method, distributed antenna system, and components that generate a jitter reduced clock signal from a binary encoded data stream transmitted over a communication medium. The method includes receiving a modulated signal that includes the binary encoded data stream and generating a recovered clock signal that is phase locked to the binary encoded data stream. The method further comprises generating a stable recovered clock signal by filtering the recovered clock signal to remove jitter, while allowing the clock signal to track long-term drift.
21 Citations
16 Claims
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1. A method of generating a jitter reduced clock signal from signal transmitted over a communication medium, the method comprising:
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receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream; generating a recovered clock signal that is phase locked to the binary encoded data stream with circuitry having a filter with a bandwidth that does not substantially block the long-term drift in the modulated signal; and generating a jitter reduced clock signal by filtering the recovered clock signal using a filtering circuit having a bandwidth narrower than the bandwidth of the circuitry that is used for generating the recovered clock signal in order to remove jitter while allowing the jitter reduced clock signal to track drift of the binary encoded data stream. - View Dependent Claims (2, 3, 4, 5)
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6. A distributed antenna system, comprising:
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a master unit that clocks a binary encoded data stream onto high speed data interface circuitry using a modulated signal based upon an output of a reference oscillator; and at least one remote unit that receives the modulated signal and binary encoded data stream from the master unit, the at least one remote unit including; a clock recovery circuit that is configured to generate a recovered clock signal that is phase-locked to the binary encoded data stream and that includes a filter configured with a bandwidth that does not substantially block the long-term drift in the modulated signal; and a filtering circuit having a bandwidth narrower than the bandwidth of the filter of the clock recovery circuit and that is configured to filter the recovered clock signal in order to remove jitter while allowing the recovered clock signal to track long-term drift of the binary encoded data stream for generating a jitter reduced clock signal. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of generating a jitter reduced clock signal from an encoded data stream, the method comprising:
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generating a recovered clock signal that is phase locked to the binary encoded data stream with circuitry having a filter with a bandwidth that does not substantially block the long-term drift in the modulated signal; clocking data from the encoded data stream into a processing unit based on the recovered clock signal; with the processing unit, using the clocked data and detecting a periodic signal component, other than the bit rate, from the clocked data of the encoded data stream; generating a reference clock signal based on the detected periodic signal component from the clocked data; and filtering the reference clock signal with a circuit having a bandwidth narrower than the bandwidth of the circuitry used for generating the recovered clock signal and that substantially blocks jitter while substantially allowing the long-term drift of the reference clock signal.
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Specification