On-chip IR drop detectors for functional and test mode scenarios, circuits, processes and systems

• US 9,081,063 B2
• Filed: 03/29/2011
• Issued: 07/14/2015
• Est. Priority Date: 11/22/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Narayanan, Prakash, Polarouthu, Sudhir
• Primary Examiner(s): Nguyen, Vincent Q
• Application Number:
  US13/074,735
• Publication Number:
  US 20120126781A1
• Time in Patent Office: 1,568 Days
• Field of Search: 324/76.11, 324/713, 713/300
• US Class Current: 1/1
• CPC Class Codes: G01R 19/257 using analogue/digital converters of the type with comparison of different reference values with the value of voltage or current, e.g. using step-by-step method
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/3181 Functional testing G01R31/3177 takes precedence
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]

Abstract

An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; and an electronic monitoring circuit (100) that has a variably operable reference circuit (150) responsive to an input register (155) and having an output, comparison circuitry (110) having plural outputs and having a first input coupled to the output of said variably operable reference circuit (150) and a set of second inputs each second input coupled to a respective one of said power grid points (30.i); and an output register (120) having at least two register bit cells (120.i) respectively fed by the plural outputs of said comparison circuitry (110.i). Other integrated circuits, and processes of testing and of manufacturing are also disclosed.

Claims

1. An integrated circuit comprising:

a functional circuit having a power grid with a set of power grid points for monitoring; and

an electronic monitoring circuit including

a variably operable reference circuit responsive to an input register and having an output;

comparison circuitry having plural outputs, and having a first input coupled to the output of said variably operable reference circuit and a set of second inputs each second input coupled to a respective one of said power grid points;

an output register having at least two register bit cells respectively fed by the plural outputs of said comparison circuitry; and

a control circuit coupled to operate said input multiplexing circuit to progressively select power grid points at least one at a time.

2. The integrated circuit claimed in claim 1 wherein said variably operable reference circuit includes a trimmable voltage reference circuit and said input register includes a trim register.

3. The integrated circuit claimed in claim 1 wherein said variably operable reference circuit includes a control circuit operable via said input register to sequentially adjust a reference for the output to the comparison circuitry.

4. The integrated circuit claimed in claim 1 further comprising a multi-bit statistics circuit coupled to at least one of the outputs of said comparison circuitry.

5. The integrated circuit claimed in claim 1 wherein said power grid includes at least one supply line and at least one semiconductor element through which current flows between the supply line and at least one of the power grid points.

6. The integrated circuit claimed in claim 1 wherein said variably operable reference circuit includes an input multiplexing circuit having inputs for the power grid points and at least one output to at least part of said comparison circuitry.

7. The integrated circuit claimed in claim 1 wherein said output register has more than two register bit cells, and is shiftable between at least two of the register bit cells to load such register bit cells sequentially with the output signals from at least one output of said comparison circuitry as the power grid points are selected by said input multiplexing circuit.

8. The integrated circuit claimed in claim 1 wherein said output register is scannable by multiple register bit cells for n-wide scan.

9. The integrated circuit claimed in claim 1 wherein said output register has more than two register bit cells, and the integrated circuit further comprising an output demultiplexing circuit having outputs to at least two of the register bit cells of said output register.

10. The integrated circuit claimed in claim 1 wherein said input circuit is structured to provide an output as a function of the difference of voltages at its first and second inputs.

11. The integrated circuit claimed in claim 1 further comprising an input multiplexer circuit having inputs coupled respectively to at least some of said power grid points and an output coupled to the first input of said input circuit.

12. The integrated circuit claimed in claim 11 further comprising a control circuit coupled to operate said input multiplexer circuit to progressively select power grid points at least one at a time.

13. The integrated circuit claimed in claim 11 wherein said input multiplexer circuit also has an input for said analog reference and has a second output, said input multiplexer circuit coupled via the two outputs to feed selected inputs pairwise to the first and second inputs of said input circuit.

14. The integrated circuit claimed in claim 11 wherein said multi-bit output interface includes at least one statistics circuit and an output multiplexer coupling said analog to digital converter circuit to said multi-bit output interface.

15. The integrated circuit claimed in claim 11 further comprising an output multiplexer coupling said analog to digital converter circuit to said multi-bit output interface, and a control circuit coupled to operate said input multiplexer circuit and said output multiplexer circuit in coordination with each other.

16. The integrated circuit claimed in claim 1 wherein said multi-bit output interface includes an output multiplexer.

17. A process of testing an integrated circuit having scan chains and a power grid, the process comprising:

scanning in a scan pattern into at least one of the scan chains;

comparing the voltage for different power grid points with a reference and providing the comparison results to scan registers;

varying the reference and repeating the comparing; and

when the comparison results satisfy a test criterion, then storing a value representing the reference thus varied as a test result;

wherein the providing of comparison results to scan registers includes data gating each register such that once it registers a comparison result indicating an excessive IR drop, it holds that result thereafter in a current run of the process for that scan pattern and value of the reference.

18. The process claimed in claim 17 wherein the varying includes trimming an analog voltage to provide the reference.

19. The process claimed in claim 17 wherein the varying includes continuing the varying according to a direction of approach to identify a worst case IR drop value as the test criterion.

20. The process claimed in claim 17 further comprising finding a reference value just at which all the power grid point voltages become greater than the reference, whereby the difference between supply voltage and the thus-found reference value indicates a worst-case IR drop.

21. The process claimed in claim 17 wherein the test criterion is approximately a greatest lower bound on the reference above which the voltages of all the power grid points being tested lie.

22. The process claimed in claim 17 further comprising operating an incrementer on-chip to trim the reference.

23. The process claimed in claim 17 further comprising compacting at least some of the scan chains to provide a compactor output, and multiplexing the compactor output with the comparison results from the scan registers.

24. An integrated circuit comprising:

a functional circuit having a power grid with a set of power grid points for monitoring; and

an electronic monitoring circuit including;

a variably operable reference circuit responsive to an input register and having an output, wherein said variably operable reference circuit includes an input multiplexing circuit having inputs for the power grid points and at least one output to at least part of said comparison circuitry;

a comparison circuitry having plural outputs, and having a first input coupled to the output of said variably operable reference circuit and a set of second inputs each second input coupled to a respective one of said power grid points; and

an output register having at least two register bit cells respectively fed by the plural outputs of said comparison circuitry.

25. The integrated circuit claimed in claim 24 wherein said variably operable reference circuit includes a trimmable voltage reference circuit and said input register includes a trim register.

26. The integrated circuit claimed in claim 24 wherein said variably operable reference circuit includes a control circuit operable via said input register to sequentially adjust a reference for the output to the comparison circuitry.

27. The integrated circuit claimed in claim 24 further comprising a multi-bit statistics circuit coupled to at least one of the outputs of said comparison circuitry.

28. The integrated circuit claimed in claim 24 wherein said power grid includes at least one supply line and at least one semiconductor element through which current flows between the supply line and at least one of the power grid points.

29. The integrated circuit claimed in claim 24 further comprising a control circuit coupled to operate said input multiplexing circuit to progressively select power grid points at least one at a time.

30. The integrated circuit claimed in claim 29 wherein said output register has more than two register bit cells, and is shiftable between at least two of the register bit cells to load such register bit cells sequentially with the output signals from at least one output of said comparison circuitry as the power grid points are selected by said input multiplexing circuit.

31. The integrated circuit claimed in claim 24 wherein said output register is scannable by multiple register bit cells for n-wide scan.

32. The integrated circuit claimed in claim 24 wherein said output register has more than two register bit cells, and the integrated circuit further comprising an output demultiplexing circuit having outputs to at least two of the register bit cells of said output register.