Hardware-based automatic clock gating

• US 9,081,517 B2
• Filed: 08/31/2011
• Issued: 07/14/2015
• Est. Priority Date: 08/31/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Koniaris, Kleanthes, de Cesare, Josh P., Millet, Timothy J., Cho, Jung Wook, Machnicki, Erik
• Primary Examiner(s): YANCHUS III, PAUL B
• Application Number:
  US13/223,282
• Publication Number:
  US 20130055004A1
• Time in Patent Office: 1,413 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method for automatically updating with hardware clock tree settings on a system-on-a-chip (SOC). A SOC includes a hardware clock control unit (HCCU) coupled to a software interface and a clock tree. The SOC also includes multiple integrated circuit (IC) devices, wherein each IC device receives one or more associated core clocks provided by one or more phase lock loops (PLLs) via the clock tree. The HCCU receives a software-initiated request specifying a given IC device is to be enabled. The HCCU identifies one or more core clocks used by the given IC device. For each one of the identified core clocks, the HCCU configures associated circuitry within the clock tree to generate an identified core clock. The HCCU may also traverse the clock tree and disable clock generating gates found not to drive any other enabled gates or IC devices.

Claims

1. A method comprising:

providing via a clock switching network (CSN) an associated one of a plurality of core clocks to each of a plurality of integrated circuit (IC) devices on a system-on-a-chip (SOC);

receiving at a hardware clock control unit (HCCU) a software-initiated request specifying a first IC device identifier corresponding to the plurality of IC devices, wherein the software-initiated request is generated at least in part responsive to an earlier indication sent by the HCCU indicating the first IC device is ready for a change in one or more core clocks;

selecting a given entry of a first table using the device identifier, wherein the first table comprises a plurality of entries and each entry of the plurality of entries associates a device identifier with one or more core clock identifiers;

identifying one or more core clock identifiers within the given entry;

for each of the one or more identified core clock identifiers, configuring circuitry within the CSN to generate an identified core clock.

2. The method as recited in claim 1, wherein for each of the one or more identified core clock identifiers, configuring circuitry within the CSN further comprises the HCCU:

identifying one or more associated clock generating gates;

for each one of the identified clock generating gates, loading parameter values corresponding to an identified core clock; and

enabling each one of the identified clock generating gates according to a timing schedule preventing an output of each one of the identified clock generating gates from changing until each corresponding input has stabilized.

3. The method as recited in claim 2, wherein the parameter values include at least one of the following:

a select value for a clock switching circuit gate and a divisor value for a clock frequency divider circuit gate.

4. The method as recited in claim 1, further comprising the HCCU:

detecting each clock corresponding to the one or more core clock identifiers is enabled; and

in response to said detection, sending an indication to a reset controller corresponding to the first IC device to begin a reset sequence for the first IC device.

5. The method as recited in claim 1, further comprising the HCCU:

receiving a software-initiated request specifying a second IC device of the plurality of IC devices is to be disabled;

identifying one or more core clocks of the plurality of core clocks used by circuitry within the second IC device; and

for each one of the identified core clocks, disable associated circuitry within the CSN to disable an identified core clock.

6. The method as recited in claim 1, further comprising using a core clock identifier of the identified core clock identifiers to access a second table, wherein the second table comprises a plurality of entries and each entry of the plurality of entries associates a core clock identifier with one or more clock gates within the CSN.

7. The method as recited in claim 1, further comprising the HCCU:

determining a given clock generating gate in a given level of the CSN has no enabled targets, wherein a target is another clock generating gate or an IC device; and

in response to said determination, disabling the given clock generating gate.

8. The method as recited in claim 7, further comprising the HCCU traversing the CSN from a bottom level to a top level when performing said determination.

9. A system-on-a-chip (SOC) comprising:

a software interface;

a plurality of phase lock loops (PLLs);

a plurality of integrated circuit (IC) devices, each configured to receive one or more associated core clocks of a plurality of core clocks provided by one or more of the plurality of PLLs via a clock switching network;

a hardware clock control unit (HCCU) coupled to the software interface and the clock switching network; and

a table comprising a plurality of entries, wherein each entry of the plurality of entries associates a device identifier with one or more core clock identifiers;

wherein the HCCU is configured to;

receive a software-initiated request specifying a first IC device identifier corresponding to the plurality of IC devices, wherein the software-initiated request is generated at least in part responsive to an earlier indication sent by the HCCU indicating the first IC device is ready for a change in one or more core clocks;

select a given entry of the table using the first IC device identifier;

identify one or more core clock identifiers within the given entry;

for each one of the one or more identified core clock identifiers, configure associated circuitry within the clock switching network (CSN) to generate an identified core clock.

10. The SOC as recited in claim 9, wherein for each of the one or more identified core clock identifiers, the HCCU is configured to:

identify one or more associated clock generating gates within the CSN;

for each one of the identified clock generating gates, load parameter values corresponding to an identified core clock; and

enable each one of the identified clock generating gates according to a timing schedule preventing an output of each one of the identified clock generating gates from changing until each corresponding input has stabilized.

11. The SOC as recited in claim 10, wherein the HCCU is further configured to read the parameter values from programmable clock configuration registers.

12. The SOC as recited in claim 9, wherein the HCCU is further configured to:

detect each clock corresponding to one or more core clock identifiers is enabled; and

in response to said detection, send an indication to a reset controller corresponding to the first IC device to begin a reset sequence for the first IC device.

13. The SOC as recited in claim 12, wherein the HCCU is further configured to:

receive an indication from the reset controller that the reset sequence is complete;

in response to said detection;

identify a subset of the identified core clocks unused after the reset sequence; and

for each one of the core clocks in the identified subset, configure associated circuitry within the CSN to disable an identified core clock.

14. The SOC as recited in claim 9, wherein the HCCU is further configured to:

receive a software-initiated request specifying a second IC device of the plurality of IC devices is to be disabled;

identify one or more core clocks of the plurality of core clocks used by circuitry within the second IC device; and

for each one of the identified core clocks, disable associated circuitry within the CSN to disable an identified core clock.

15. The SOC as recited in claim 9, wherein the HCCU is further configured to use a core clock identifier of the identified core clock identifiers to access a second table, wherein the second table comprises a plurality of entries and each entry of the plurality of entries associates a core clock identifier with one or more clock gates within the CSN.

16. The SOC as recited in claim 9, wherein the HCCU is further configured to:

determine a given clock generating gate in a given level of the CSN has no enabled targets, wherein a target is another clock generating gate or an IC device; and

in response to said determination, disable the given clock generating gate.

17. A hardware clock control unit (HCCU) on a system-on-a-chip (SOC) comprising:

a first interface configured to receive software-initiated requests;

a second interface coupled to a clock switching network (CSN) configured to provide an associated one of a plurality of core clocks to each of a plurality of integrated circuit (IC) devices on a system-on-a-chip (SOC);

a table comprising a plurality of entries, wherein each entry of the plurality of entries associates a device identifier with one or more core clock identifiers;

wherein the control logic is configured to;

receive a software-initiated request specifying a first IC device identifier corresponding to the plurality of IC devices, wherein the software-initiated request is generated at least in part responsive to an earlier indication sent by the HCCU indicating the first IC device is ready for a change in one or more core clocks;

select a given entry of the table using the first IC device identifier;

identify one or more core clock identifiers within the given entry;

for each one of the one or more identified core clock identifiers, configure associated circuitry within the clock switching network (CSN) to generate an identified core clock.

18. The HCCU as recited in claim 17, wherein for each of the one or more identified core clock identifiers, the control logic is configured to:

identify one or more associated clock generating gates within the CSN;

for each one of the identified clock generating gates, load parameter values corresponding to an identified core clock; and

enable each one of the identified clock generating gates according to a timing schedule preventing an output of each one of the identified clock generating gates from changing until each corresponding input has stabilized.

19. The HCCU as recited in claim 17, wherein the control logic is further configured to:

receive a software-initiated request specifying a second IC device of the plurality of IC devices is to be disabled;

identify one or more core clocks of the plurality of core clocks used by circuitry within the second IC device; and

for each one of the identified core clocks, disable associated circuitry within the CSN to disable an identified core clock.

20. The HCCU as recited in claim 19, wherein the control logic is further configured to:

determine a given clock generating gate in a given level of the CSN has no enabled targets, wherein a target is another clock generating gate or an IC device; and

in response to said determination, disable the given clock generating gate.