Multiple processor system and method including multiple memory hub modules

• US 9,082,461 B2
• Filed: 08/07/2012
• Issued: 07/14/2015
• Est. Priority Date: 08/28/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): MISIURA, BRIAN THOMAS
• Application Number:
  US13/568,447
• Publication Number:
  US 20120303885A1
• Time in Patent Office: 1,071 Days
• Field of Search: 710/317, 711/117, 711/170
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00

Abstract

A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Claims

1. A computer system comprising:

a plurality of devices capable of making memory requests, the devices selected from the group consisting of processors and direct memory access devices;

a plurality of memory modules in communication with the plurality of devices, the memory modules each comprising a plurality of memory devices and a memory hub, the memory hub comprising;

a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices in the memory module; and

a switch coupled to;

i) a plurality of first access ports each of the plurality of first access ports coupled to a different one of the plurality of devices capable or making memory requests;

ii) a plurality of second access ports each being coupled to a respective one of a plurality of third access ports external to the memory module; and

iii) a plurality of the memory controllers, wherein, in response to an output from a corresponding one of the plurality of devices capable of making memory requests, the switch is configured to selectively couple one of the plurality of the first access ports that receives the output from the corresponding one of the plurality of devices capable of making memory requests memory requester to either;

one of the second access ports or one of the memory ports.

2. The computer system of claim 1 wherein each of the memory devices comprises a dynamic random access memory device.

3. The computer system of claim 1 wherein each of the memory hubs further comprises a respective cache memory device associated with each of the memory controllers, each of the cache memory devices being operable to store data that is accessed through a respective one of the memory access ports coupled to the switch.

4. The computer system of claim 1 wherein the memory controllers and the switch are fabricated as a common integrated circuit in a semiconductor substrate.

5. The computer system of claim 1 wherein the memory devices and the memory hub are fabricated as a common integrated circuit in a semiconductor substrate.

6. The computer system of claim 1 wherein the memory hub further comprises a respective write buffer associated with each of the memory controllers, each of the write buffers being configured to receive write data and associated write addresses through a respective one of the memory ports of the switch and to store the write data and addresses for subsequent coupling to a respective one of the memory controllers.

7. The computer system of claim 6 wherein each of the write buffers is configured to accumulate write data and addresses for a plurality of write memory accesses and to then sequentially couple the plurality of write data and addresses to a respective one of the memory controllers without any intervening read memory accesses.

8. The computer system of claim 1 wherein each of the memory hubs further comprises a direct memory access device coupled to the switch and the memory controllers, the direct memory access device being configured to cause the switch and each of the memory controllers to perform memory write and read accesses.

9. A computer system, comprising:

a plurality of devices capable of making memory requests;

a first plurality of memory modules coupled to the devices capable of making memory requests, the memory modules in the first plurality each comprising a first set of memory ports coupled to a respective one of the plurality of devices capable of making memory requests, the memory modules in the first plurality further including a second set of memory ports, each of the memory modules in the first plurality further comprising a plurality of memory devices; and

a second plurality of memory modules each comprising at least one memory port coupled to a memory module in the first plurality through a memory port in the second set, each of the memory modules in the second plurality including a plurality of memory devices, each of the memory modules in the second plurality being accessed by at least one of the devices capable of making memory requests through at least one of the memory modules in the first plurality, the memory modules in the first plurality being configured to allow the number of memory modules in the first plurality through which the at least one memory module in the second plurality of memory modules is accessed to be adjustable to vary the data bandwidth between at least one of the devices capable of making memory requests and the at least one memory module in the second plurality of memory modules.

10. The computer system of claim 9 wherein the number of ports in each of the modules in the second plurality of memory modules corresponds in number to the number of modules in the first plurality of memory modules.

11. The computer system of claim 9 wherein the number of ports in of each module of the first plurality of memory modules corresponds in number to the number of devices capable of making memory requests.