Apparatuses and methods including memory array and data line architecture

• US 9,082,485 B2
• Filed: 11/25/2013
• Issued: 07/14/2015
• Est. Priority Date: 07/27/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US14/089,337
• Publication Number:
  US 20140078827A1
• Time in Patent Office: 596 Days
• Field of Search: 365/185.05, 365/51, 365/63, 365/130, 365/185.18, 365/230.03
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.

Claims

1. A device comprising:

a first memory array located over a substrate;

first data lines located between the substrate and the first memory array;

a second memory array located over the substrate;

second data lines located between the substrate and the second memory array;

additional data lines located over the first and second memory arrays;

a first circuit to selectively couple first memory cells of the first memory array to the additional data lines through at least a portion of the first data lines; and

a second circuit to selectively couple second memory cells of the second memory array to the additional data lines through at least a portion of the second data lines, wherein at least a portion of each of the first and second circuit is located in the substrate.

2. The device of claim 1, wherein the additional data lines include global data lines associated with the first and second memory arrays.

3. The device of claim 2, wherein the first data lines include local data lines associated with the first memory array.

4. The device of claim 2, wherein the second data lines include local data lines associated with the second memory array.

5. The device of claim 1, further comprising array data lines associated with the first memory cells, and the first circuit is configured to selectively couple the array data lines to the first data lines.

6. The device of claim 5, wherein the array data lines are located between the first data lines and the first memory cells.

7. The device of claim 1, further comprising array data lines associated with the second memory cells, and the second circuit is configured to selectively couple the array data lines to the second data lines.

8. The device of claim 7, wherein the array data lines are located between the second data lines and the second memory cells.

9. A device comprising:

a first memory array including a first memory cell string;

a first transistor including at least a portion located in a substrate of the device;

a first data line coupled to the first transistor and the first memory cell string, the first data line located between the first transistor and the first memory cell string;

a first additional data line coupled to the first transistor, the first additional data line located between the first transistor and the first data line;

a second memory array including a second memory cell string;

a second transistor including at least a portion located in the substrate;

a second data line coupled to the second transistor and the second memory cell string, the second data line located between the second transistor and the second memory cell string;

a second additional data line coupled to the second transistor, the second additional data line located between the second transistor and the second data line; and

a third additional data line coupled to the first and second additional data lines, wherein the first memory cell string is located between the first data line and the third additional data line.

10. The device of claim 9, wherein the second memory cell string is located between the second data line and the third additional data line.

11. The device of claim 9, wherein the first data line includes an array data line associated with the first memory array.

12. The device of claim 9, wherein the second data line includes an array data line associated with the second memory array.

13. The device of claim 9, wherein the first additional data line includes a local data line associated with the first memory array.

14. The device of claim 9, wherein the second additional data line includes a local data line associated with the second memory array.

15. The device of claim 9, wherein the third additional data line includes a global data line associated with the first and second memory arrays.

16. A method comprising:

forming a first circuit and a second circuit such that at least a portion of each of the first and second circuit is located in a substrate;

forming first data lines over the first circuit;

forming first a memory array over the first data lines;

forming second data lines over the second circuit;

forming a second memory array over the second data lines; and

forming additional data lines over the first and second memory arrays, such that at least one of the additional data lines is coupled to one of the first data lines and one of the second data lines.

17. The method of claim 16, wherein forming the first circuit includes forming a transistor such that a first node of the transistor is coupled to one of the first data lines.

18. The method of claim 17, wherein forming the second circuit includes forming an additional transistor such that a first node of the additional transistor is coupled to one of the second data lines.

19. The method of claim 16, further comprising:

forming array data lines over the first data lines such that the array data lines are between first data lines and the first memory array.

20. The method of claim 19, wherein forming the first circuit includes forming a transistor such that a first node of the transistor is coupled to one of the first data lines and a second node of the transistor is coupled to one of the array data lines.

21. The method of claim 20, further comprising:

forming additional array data lines over the second data lines such that the additional array data lines are between second data lines and second memory array.

22. The method of claim 21, wherein forming the second circuit includes forming an additional transistor such that a first node of the additional transistor is coupled to one of the second data lines and a second node of the additional transistor is coupled to one of the additional array data lines.