Non-volatile memory
First Claim
1. A non-volatile memory, comprising:
- a memory array comprising m×
n memory cells, wherein the memory array is connected with m word lines, n source lines and n bit lines;
a row decoder connected with the m word lines for enabling one of the m word lines, thereby determining a selected row of n memory cells, wherein the n memory cells in the selected row are connected with the n source lines and the n bit lines;
a source line decoder connected with the n source lines, wherein by the source line decoder, an x-th source line of the n source lines is connected with a source line voltage but the other source lines of the n source lines are in a floating state;
a column decoder connected with the n bit lines, wherein by the column decoder, an x-th bit line of the n bit lines is connected with a data line but the other bit lines of the n bit lines are connected with a reference voltage; and
a sensing circuit connected with the column decoder through the data line, wherein the sensing circuit determines a storing state of a selected memory cell according to a memory current flowing through the data line,wherein x is a positive integer and 1≦
x≦
n.
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Accused Products
Abstract
A non-volatile memory includes a memory array, a row decoder, a source line decoder, a column decoder, and a sensing circuit. The memory array is connected with m word lines, n source lines and n bit lines. The row decoder determines a selected row of n memory cells. The n memory cells in the selected row are connected with the n source lines and the n bit lines. By the source line decoder, an x-th source line is connected with a source line voltage but the other source lines of the n source lines are in a floating state. By the column decoder, an x-th bit line of the n bit lines is connected with a data line but the other bit lines are connected with a reference voltage. The sensing circuit determines a storing state of a selected memory cell.
12 Citations
11 Claims
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1. A non-volatile memory, comprising:
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a memory array comprising m×
n memory cells, wherein the memory array is connected with m word lines, n source lines and n bit lines;a row decoder connected with the m word lines for enabling one of the m word lines, thereby determining a selected row of n memory cells, wherein the n memory cells in the selected row are connected with the n source lines and the n bit lines; a source line decoder connected with the n source lines, wherein by the source line decoder, an x-th source line of the n source lines is connected with a source line voltage but the other source lines of the n source lines are in a floating state; a column decoder connected with the n bit lines, wherein by the column decoder, an x-th bit line of the n bit lines is connected with a data line but the other bit lines of the n bit lines are connected with a reference voltage; and a sensing circuit connected with the column decoder through the data line, wherein the sensing circuit determines a storing state of a selected memory cell according to a memory current flowing through the data line, wherein x is a positive integer and 1≦
x≦
n. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification