Semiconductor memory device storing refresh period information and operating method thereof

• US 9,082,504 B2
• Filed: 07/05/2013
• Issued: 07/14/2015
• Est. Priority Date: 07/12/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jung-Sik, Lee, Jung-Bae
• Primary Examiner(s): Lam, David
• Application Number:
  US13/936,057
• Publication Number:
  US 20140016421A1
• Time in Patent Office: 739 Days
• Field of Search: 365/222, 365/233.1, 365/230.06, 365/230.08
• US Class Current: 1/1
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413

Abstract

A semiconductor memory device which stores refresh period information thereby adjusting a refresh period and a method of operating the same. The semiconductor memory device includes a cell array and a refresh information storing unit. The cell array includes one or more cell regions each having a plurality of memory cells. The refresh information storing unit is configured to store first information including a first refresh period and second information including a second refresh period in correspondence to each of the cell regions. Memory cells included in each of the cell regions are refreshed at the first refresh period according to the first information in a first refresh time band and are refreshed at the second refresh period according to the second information in a second refresh time band.

Claims

1. A semiconductor memory device comprising:

a cell array comprising one or more cell regions each having a plurality of memory cells; and

a refresh information storing unit configured to store first information including a first refresh period, and second information including a second refresh period in correspondence to each of the cell regions,

wherein memory cells included in each of the cell regions are refreshed at the first refresh period according to the first information in a first refresh time band and are refreshed at the second refresh period according to the second information in a second refresh time band.

2. The semiconductor memory device of claim 1, wherein each of the cell regions is a page selectively accessed in response to a row address signal.

3. The semiconductor memory device of claim 1, wherein the first refresh time band is a refresh time band corresponding to a case where memory cells included in each of the cell regions are in a dynamic state, and

wherein the second refresh time band is a refresh time band corresponding to a case where the memory cells included in each of the cell regions are in a static state.

4. The semiconductor memory device of claim 1, wherein the first refresh time band is a refresh time band corresponding to a case where the semiconductor memory device is in an auto-refresh mode, and

wherein the second refresh time band is a refresh time band corresponding to a case where the semiconductor memory device is in a self-refresh mode.

5. The semiconductor memory device of claim 1, further comprising a size information storage unit configured to store a third information regarding sizes of each of the cell regions,

wherein a refresh period of each of the cell regions is adjusted based on the first, second, and third information.

6. The semiconductor memory device of claim 1, wherein retention characteristics of each of the cell regions are categorized into n groups, and

wherein each of the first information and the second information has a value selected from among the n groups.

7. The semiconductor memory device of claim 1, wherein memory cells included in each of the cell regions are refreshed based on either a first address from an internal counter or a second address received from outside the semiconductor memory device, and

wherein a refresh period of each of the cell regions is adjusted based on the number of times that the second address is input to the semiconductor memory device.

8. The semiconductor memory device of claim 1, wherein each of the cell regions is refreshed in response to a signal received from an external controller, and

wherein the first information and the second information corresponding to each of the cell regions are output to outside the semiconductor memory device.

9. The semiconductor memory device of claim 1, wherein the refresh information storing unit includes a fuse array or registers.

10. The semiconductor memory device of claim 1, wherein the first information and the second information are sequentially output in response to a signal from an external controller.

11. A semiconductor memory device comprising:

a cell array comprising one or more cell regions each having a plurality of memory cells;

a refresh information storing unit configured to store information regarding refresh periods corresponding to the respective cell regions;

a refresh counter configured to output a first address for refreshing a first memory cell included in a first cell region of the cell array when the semiconductor memory device receives a first command; and

an address selecting unit configured to select a second address received from outside the semiconductor memory device and to refresh a second memory cell included in a second cell region of the cell array when the semiconductor memory device receives a second command.

12. The semiconductor memory device of claim 11, wherein the second memory cell included in the second cell region is refreshed at least twice during a single refresh period.

13. The semiconductor memory device of claim 12, wherein the cell region of the cell array comprises one or more banks,

wherein the semiconductor memory device is configured to operate in a first configuration, a second configuration, or a third configuration in response to a signal from the memory controller,

wherein in the first configuration, the semiconductor memory device is configured to refresh memory cells of the cell array regardless of the second command,

wherein in the second configuration, the semiconductor memory device is configured to refresh the memory cells of the cell array regardless of bank addresses included in the second address when the second command is received, and

wherein in the third configuration, the semiconductor memory device is configured to refresh the memory cells of the cell array in response to both the second command and the second address.

14. The semiconductor memory device of claim 11, wherein the first command indicates an auto-refresh command and the second command indicates a designated refresh command.

15. The semiconductor memory device of claim 11, wherein memory cells included in the first cell region are in a static state and memory cells included in the second cell region are in a dynamic state.

16. A semiconductor memory device comprising:

a cell array comprising a plurality of cell regions each having a plurality of memory cells; and

a refresh information storing unit configured to store refresh information including a plurality of retention characteristic values, each retention characteristic value indicating one or more bits,

wherein memory cells included in a first cell region of the cell regions are refreshed at the first refresh period and memory cells included in a second cell region of the cell regions are refreshed at the second refresh period greater than the first refresh period.

17. The semiconductor memory device of claim 16, wherein each of the first and second cell regions includes at least one page selectively accessed in response to a row address signal.

18. The semiconductor memory device of claim 16, wherein the refresh information is output to a memory controller outside the semiconductor memory device through an input/output path of a data signal DQ.

19. The semiconductor memory device of claim 16, wherein the memory cells to be refreshed are in a dynamic state or in a static state.

20. The semiconductor memory device of claim 16, wherein the memory cells to be refreshed are associated with an auto-refresh mode or a self-refresh mode of the semiconductor memory device.