Semiconductor device and manufacturing method thereof

• US 9,082,663 B2
• Filed: 09/10/2012
• Issued: 07/14/2015
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Isobe, Atsuo, Sasaki, Toshinari
• Primary Examiner(s): Gurley, Lynne
• Assistant Examiner(s): Webb, Vernon P
• Application Number:
  US13/608,042
• Publication Number:
  US 20130069054A1
• Time in Patent Office: 1,037 Days
• Field of Search: 257/40, 257/43, 257/52, 257/57, 257/59, 257/72, 257/E21.409, 257/E29.255, 438/104
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

In a semiconductor device including an oxide semiconductor layer, a conductive layer is formed in contact with a lower portion of the oxide semiconductor layer and treatment for adding an impurity is performed, so that a channel formation region and a pair of low-resistance regions between which the channel formation region is sandwiched are formed in the oxide semiconductor layer in a self-aligned manner. Wiring layers electrically connected to the conductive layer and the low-resistance regions are provided in openings of an insulating layer.

Claims

1. A semiconductor device comprising:

a first conductive layer;

a first insulating layer whose side surface is in contact with a side surface of the first conductive layer;

an oxide semiconductor layer over and in contact with the first conductive layer and the first insulating layer;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode layer over the oxide semiconductor layer with the gate insulating layer interposed therebetween;

a second insulating layer over the gate electrode layer;

a first wiring layer over the second insulating layer, the first wiring layer being in contact with the first conductive layer through a first opening of the second insulating layer;

a second wiring layer over the second insulating layer, the second wiring layer being in contact with the oxide semiconductor layer through a second opening of the second insulating layer; and

a third wiring layer over the second insulating layer, the third wiring layer electrically connected to the oxide semiconductor layer through a third opening of the second insulating layer,

wherein one surface of the oxide semiconductor layer is directly in contact with the first conductive layer.

2. The semiconductor device according to claim 1,

wherein the second wiring layer is in contact with a first portion of the oxide semiconductor layer,

wherein the gate electrode layer overlaps with a second portion of the oxide semiconductor layer, and

wherein the first portion is thinner than the second portion.

3. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer comprises a first region, a second region, and a channel formation region between the first region and the second region,

wherein the channel formation region overlaps with the gate electrode layer, and

wherein each of a resistivity of the first region and a resistivity of the second region is lower than a resistivity of the channel formation region.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises a c-axis-aligned crystal region.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn-based oxide semiconductor.

6. The semiconductor device according to claim 1, wherein the first wiring layer and the second wiring layer are branched from one wiring.

7. A semiconductor device comprising:

a base insulating layer;

a first conductive layer whose bottom surface and side surface are provided in the base insulating layer and upper surface is exposed from the base insulating layer;

an oxide semiconductor layer over the base insulating layer and the first conductive layer, the oxide semiconductor layer including a first low-resistance region, a second low-resistance region, and a channel formation region between the first low-resistance region and the second low-resistance region, wherein the channel formation region is in contact with the base insulating layer and the first low-resistance region is in contact with the first conductive layer;

a gate insulating layer over the first conductive layer, the oxide semiconductor layer, and the base insulating layer;

a gate electrode layer over the gate insulating layer and overlapping with the channel formation region;

an insulating layer over the gate insulating layer and the gate electrode layer;

a first wiring layer in a first opening that overlaps with the first conductive layer and reaches the first conductive layer and reaches the first low-resistance region, the first wiring layer being in contact with the first conductive layer;

a second wiring layer in a second opening that overlaps with the first low-resistance region and reaches the first low-resistance region, the second wiring layer being in contact with the first low-resistance region; and

a third wiring layer in a third opening, the third wiring layer electrically connected to the second low-resistance region,

wherein one surface of the oxide semiconductor layer is directly in contact with the first conductive layer.

8. The semiconductor device according to claim 7, wherein the third opening faces to the second opening with the gate electrode layer interposed therebetween.

9. The semiconductor device according to claim 7,

wherein the third opening overlaps with the second low-resistance region and reaches the second low-resistance region, and

wherein the third wiring layer is in contact with the second low-resistance region.

10. The semiconductor device according to claim 7, further comprising:

a second conductive layer whose bottom surface and side surface are provided in the base insulating layer and upper surface is exposed from the base insulating layer,

wherein the oxide semiconductor layer is provided over the second conductive layer,

wherein the second low-resistance region is in contact with the second conductive layer,

wherein the third opening overlaps with the second conductive layer and reaches the second conductive layer, and

wherein the third wiring layer is in contact with the second conductive layer.

11. The semiconductor device according to claim 7, further comprising:

a second conductive layer whose bottom surface and side surface are provided in the base insulating layer and upper surface is exposed from the base insulating layer,

wherein the oxide semiconductor layer is provided over the second conductive layer,

wherein the second low-resistance region is in contact with the second conductive layer,

wherein the second opening overlaps with the first conductive layer,

wherein the third opening overlaps with the second conductive layer and the second low-resistance region and reaches the second low-resistance region, and

wherein the third wiring layer is in contact with the second low-resistance region.

12. The semiconductor device according to claim 7, further comprising:

a second conductive layer whose bottom surface and side surface are provided in the base insulating layer and upper surface is exposed from the base insulating layer,

wherein the oxide semiconductor layer is provided over the second conductive layer,

wherein the second low-resistance region is in contact with the second conductive layer,

wherein the second opening overlaps with the first conductive layer,

wherein the third opening overlaps with the second conductive layer and the second low-resistance region and reaches the second conductive layer, and

wherein the third wiring layer is in contact with the second conductive layer.

13. The semiconductor device according to claim 7, wherein the oxide semiconductor layer comprises a c-axis-aligned crystal region.

14. The semiconductor device according to claim 7, wherein the same potential is supplied to the first wiring layer and the second wiring layer.

15. The semiconductor device according to claim 7, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn-based oxide semiconductor.