Use of etch process post wordline definition to improve data retention in a flash memory device

• US 9,082,714 B2
• Filed: 09/22/2011
• Issued: 07/14/2015
• Est. Priority Date: 09/22/2011
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Koval, Randy J., Hineman, Max F., Weimer, Ronald A., Shamanna, Vinayak K., Graettinger, Thomas M., Kueber, William R., Larsen, Christopher, Schrinsky, Alex J.
• Primary Examiner(s): CHOUDHRY, MOHAMMAD M
• Application Number:
  US13/993,444
• Publication Number:
  US 20130264628A1
• Time in Patent Office: 1,391 Days
• Field of Search: 257/305, 438/421
• US Class Current: 1/1
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Embodiments of the present disclosure are directed towards use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.

Claims

1. A method comprising:

forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having a first electrically insulative material formed on the control gate;

depositing a second electrically insulative material to form a liner on a surface of the individual wordline structures, on sidewall surfaces of the control gate and the cap, and on a top surface of the cap; and

etching the liner to remove at least a portion of the liner using an anisotropic dry etch process to substantially remove the second electrically insulative material of the liner from the top surface of the cap, wherein the etching reduces a thickness of the second electrically insulative material of the liner on the sidewall surfaces of the individual wordline structures such that the second electrically insulative material of the liner substantially covers the sidewall surfaces of the individual wordline structures subsequent to the etching,

wherein the substrate includes a semiconductor material, a tunnel dielectric is disposed on the semiconductor material and wherein the etching removes a portion of the tunnel dielectric and the semiconductor material of the substrate and

subsequent to etching the liner, forming an air gap between the individual wordline structures of the plurality of wordline structures.

2. The method of claim 1, wherein forming the plurality of wordline structures includes:

depositing the electrically conductive material to form a control gate layer on a charge storage node layer formed on the substrate;

depositing the first electrically insulative material on the control gate layer to form a cap layer coupled with the control gate layer; and

removing at least a portion of the cap layer, the control gate layer, and the charge storage node layer to define the plurality of wordline structures and a plurality of charge storage nodes.

3. The method of claim 1, wherein the etching reduces a thickness of the second electrically insulative material of the liner on the sidewall surfaces of the individual wordline structures to a thickness of 20 Angstroms to 30 Angstroms.

4. The method of claim 1, wherein forming the air gap includes:

selectively depositing a third electrically insulative material on a top surface of the cap such that the third electrically insulative material deposited on the top surface of the cap bridges air disposed between the individual wordline structures to form the air gap between the individual wordline structures.

5. The method of claim 1, wherein:

the liner includes silicon oxide (SiO₂) or silicon nitride (SiN);

the cap includes silicon oxide (SiO₂) or silicon nitride (SiN);

the control gate includes a metal; and

the substrate includes silicon (Si).