Semiconductor device including a counter layer, for power conversion and method of manufacturing the same

• US 9,082,812 B2
• Filed: 03/15/2012
• Issued: 07/14/2015
• Est. Priority Date: 03/16/2011
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Onozawa, Yuichi, Shiigi, Takashi
• Primary Examiner(s): Nguyen, Thanh T
• Application Number:
  US13/703,797
• Publication Number:
  US 20130082301A1
• Time in Patent Office: 1,216 Days
• Field of Search: 257341-342, 257330-331
• US Class Current: 1/1
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 27/0664 Vertical bipolar transistor in combination with diodes
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]

Abstract

A p-type base layer is selectively formed on a surface of an n-type drift layer; an n-type source layer is selectively formed on a surface of the p-type base layer; and a p-type contact layer is formed to be in contact with the selectively-formed n-type source layer. A p-type counter layer is formed to be in contact with the n-type source layer, so as to overlap the p-type contact layer, so as to be separated from an interface where the p-type base layer and the gate oxide film are in contact with each other, and to be shallower than the p-type base layer. Accordingly, switching destruction caused by process defects in an insulated gate semiconductor device is reduced.

Claims

1. A semiconductor device comprising:

a drift layer which includes a first conductivity type semiconductor substrate;

a second conductivity type base layer which is selectively formed on a surface of a first principal plane of the semiconductor substrate;

a first conductivity type source layer which is selectively formed on a surface of the base layer;

a second conductivity type contact layer which is formed to be in contact with the source layer on the first principal plane side of the base layer and which has a concentration higher than that of the base layer;

a gate electrode which is formed so as to face the drift layer, the base layer, and the source layer through an insulating film;

an emitter electrode which is formed on the first principal plane so as to be electrically connected to the source layer; and

an interlayer insulating film which is formed on the first principal plane of the semiconductor substrate to be interposed between the gate electrode and the emitter electrode so as to insulate the gate electrode and the emitter electrode,

wherein the semiconductor device further includes a second conductivity type counter layer which is formed to be in contact with the source layer and to overlap the contact layer and which is formed to be shallower than the base layer and to have a high concentration,

wherein a total doping amount per unit area of the counter layer is larger than 10% of a total doping amount per unit area of the contact layer,

wherein the depth of the counter layer is shallower than the depth of the contact layer;

wherein the depth of the counter layer is deeper than the depth of the source layer, and

wherein a sum of the total doping amount per unit area of the counter layer and the total doping amount per unit area of the contact layer is larger than that of the source layer.

2. The semiconductor device according to claim 1, wherein the total doping amount per unit area of the counter layer is larger than that of the contact layer.

3. The semiconductor device according to claim 2, wherein a sum of the total doping amount per unit area of the counter layer and the total doping amount per unit area of the contact layer is larger than that of the source layer.

4. The semiconductor device according to claim 1, wherein the total doping amount per unit area of the counter layer is larger than that of the source layer.

5. The semiconductor device according to claim 1, wherein the counter layer is formed so as to be self-aligned with a position of an opening portion of the interlayer insulating film.

6. The semiconductor device according to claim 1, wherein a plurality of the counter layers are installed.

7. The semiconductor device according to claim 1, wherein the semiconductor device is an IGBT.

8. The semiconductor device according to claim 1, wherein the semiconductor device is a trench gate-type IGBT.

9. The semiconductor device according to claim 1, wherein a shape of a cross section of pn junction between the counter layer and the source layer includes a portion of the counter layer which is convex extending to the inside of the source layer.

10. The semiconductor device according to claim 1, wherein an impurity concentration of the counter layer is higher than an impurity concentration of the contact layer.

11. The semiconductor device according to claim 1, wherein the counter layer is sandwiched between two source layers and contacts the source layers with a side being convex extending to the two source layers.

12. The semiconductor device according to claim 1, wherein a depth of a maximum concentration of the counter layer and a depth of a maximum concentration of the contact layer are each greater than a depth of the source layer.