Silver-to-silver bonded IC package having two ceramic substrates exposed on the outside of the package

• US 9,082,879 B2
• Filed: 02/15/2015
• Issued: 07/14/2015
• Est. Priority Date: 12/31/2012
• Status: Active Grant

• Current Assignee: Littelfuse Incorporated
• Original Assignee: IXYS Corporation (Littelfuse Incorporated)
• Inventors: Zommer, Nathan
• Primary Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US14/622,869
• Publication Number:
  US 20150162304A1
• Time in Patent Office: 149 Days
• Field of Search: 257/762, 257/772, 438/118, 438/644, 438/654, 438/686, 438/688
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03312 Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
• CPC Class Codes: H01L 2224/0332 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03505 Sintering
• CPC Class Codes: H01L 2224/0381 Cleaning, e.g. oxide removal step, desmearing
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05794 with a principal constituent of the material being a liquid not provided for in groups H01L2224/057 - H01L2224/05791
• CPC Class Codes: H01L 2224/05839 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08245 the item being metallic
• CPC Class Codes: H01L 2224/09181 On opposite sides of the body
• CPC Class Codes: H01L 2224/27312 Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
• CPC Class Codes: H01L 2224/2745 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/29139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/32227 the layer connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/33181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/80439 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/8084 : Sintering
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3735 : Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49844 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/05432 : Al2O3
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/20107 : Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K

Abstract

A packaged power device involves no soft solder and no wire bonds. The direct-bonded metal layers of two direct metal bonded ceramic substrate assemblies, such as Direct Bonded Aluminum (DBA) substrates, are provided with sintered silver pads. Silver nanoparticle paste is applied to pads on the frontside of a die and the paste is sintered to form silver pads. Silver formed by an evaporative process covers the backside of the die. The die is pressed between the two DBAs such that direct silver-to-silver bonds are formed between sintered silver pads on the frontside of the die and corresponding sintered silver pads of one of the DBAs, and such that a direct silver-to-silver bond is formed between the backside silver of the die and a sintered silver pad of the other DBA. After leadforming, leadtrimming and encapsulation, the finished device has exposed ceramic of both DBAs on outside package surfaces.

Claims

1. A method, comprising:

(a) attaching a sintered silver pad of a first Direct Metal Bonded (DMB) ceramic substrate assembly to a layer of silver that covers a backside of a semiconductor die such that a silver-to-silver bond is formed between the first DMB ceramic substrate and the die, wherein the die comprises the layer of silver on the backside of the die, and wherein the die further comprises a plurality of sintered silver pads on a frontside of the die; and

(b) attaching a plurality of sintered silver pads of a second DMB ceramic substrate assembly to the plurality of sintered silver pads on the frontside of the semiconductor die such that a plurality of silver-to-silver bonds is formed between the second DMB ceramic substrate assembly and the die.

2. The method of claim 1, further comprising:

(c) applying an amount of encapsulant to the first and second DMB ceramic substrate assemblies thereby forming a body portion of a package; and

(d) trimming a first plurality of leads attached to the first DMB ceramic assembly, and trimming a second plurality of leads attached to the second direct bonded ceramic assembly, such that the first and second pluralities of leads form a single in-line set of package terminals that extends from the body portion of the package.

3. The method of claim 2, wherein a surface of the first DMB ceramic substrate assembly is a first surface of the body portion, and wherein a surface of the second DMB ceramic substrate assembly is a second surface of the body portion.

4. The method of claim 1, wherein the forming of the silver-to-silver bond in (a) involves pressing the die and the first DMB ceramic substrate assembly together at an elevated temperature of at least 250 degrees Celsius, and wherein the forming of the silver-to-silver bonds in (b) involves pressing the die and the second DMB ceramic substrate assembly together at an elevated temperature of at least of at least 250 degrees Celsius.

5. The method of claim 1, further comprising:

(c) forming the semiconductor die, wherein the forming of (c) occurs before the attaching of (a) and occurs before the attaching of (b).

6. The method of claim 5, wherein the forming of the semiconductor die in (c) involves:

(c1) depositing a layer of silver onto an entire backside of a wafer using an evaporative deposition process;

(c2) after the depositing of (c1) printing silver nanoparticle paste onto selected portions of a frontside of the wafer;

(c3) sintering the silver nanoparticle paste on the frontside of the wafer thereby forming the plurality of sintered silver pads; and

(c4) dicing the wafer thereby forming the semiconductor die.

7. The method of claim 6, wherein the selected portions of the frontside of the wafer to which the silver nanoparticle paste is applied in (c2) are aluminum pads that are covered with thin layers of aluminum oxide.

8. The method of claim 1, wherein the first DMB ceramic substrate assembly is a Direct Bonded Copper (DBC) substrate assembly.

9. The method of claim 1, wherein the first DMB ceramic substrate assembly is a Direct Bonded Aluminum (DBA) substrate assembly.

10. The method of claim 1, further comprising:

(c) encapsulating the first and second DMB ceramic substrate assemblies to form a packaged power device such that a surface of the first DMB ceramic substrate forms an outside surface of the packaged power device and such that a surface of the second DMB ceramic substrate forms another outside surface of the packaged power device.

11. The method of claim 10, wherein the packaged power device comprises no soft solder and no bond wires.

12. The method of claim 1, further comprising:

(c) depositing the layer of silver on the backside of the semiconductor die using an evaporative deposition process, wherein the depositing of (c) occurs before the attaching of (a) and the attaching of (b).

13. The method of claim 1, further comprising:

(c) depositing a layer of silver on the backside of a semiconductor wafer using an evaporative deposition process;

(d) dicing the semiconductor wafer to form the semiconductor die, wherein the depositing of (c) and the dicing of (d) occur before the attaching of (a) and the attaching of (b).

14. The method of claim 1, further comprising:

(c) ink-jet printing silver nanoparticle paste onto selected portions of the frontside of the die; and

(d) sintering the silver nanoparticle paste on the frontside of the die to form the plurality of sintered silver pads, wherein the ink-jet printing of (c) and the sintering of (d) occur before the attaching of (a) and the attaching of (b).

15. The method of claim 1, wherein the semiconductor die further comprises a plurality of aluminum pads disposed on the frontside of the die, and wherein each of the plurality of sintered silver pads that is disposed on the frontside of the die is disposed on a corresponding one of the plurality of aluminum pads.

16. A method, comprising:

depositing a layer of silver onto a backside of a semiconductor die using an evaporative deposition process;

printing silver nanoparticle paste onto selected portions of a frontside of the semiconductor die;

sintering the silver nanoparticle paste on the frontside of the semiconductor die to form a plurality of sintered silver pads;

forming a silver-to-silver bond between a first Direct Metal Bonded (DMB) ceramic substrate and the semiconductor die by attaching a sintered silver pad of the first DMB ceramic substrate to the layer of silver on the backside of the semiconductor die; and

forming a plurality of silver-to-silver bonds between a second DMB ceramic substrate and the semiconductor die by attaching a plurality of sintered silver pads of the second DMB ceramic substrate to the plurality of sintered silver pads on the frontside of the semiconductor die.

17. The method of claim 16, further comprising:

encapsulating the first and second DMB ceramic substrates to form a packaged power device such that a surface of the first DMB ceramic substrate forms an outside surface of the packaged power device and such that a surface of the second DMB ceramic substrate forms another outside surface of the packaged power device.

18. The method of claim 17, wherein the packaged power device comprises no soft solder and no bond wires.

19. The method of claim 17, wherein a bent strip of leadframe metal is disposed entirely within the packaged power device, wherein the bent strip has a first end that is welded to the first DBM ceramic substrate, and wherein the bent strip has a second end that is welded to the second DBM ceramic substrate.

20. The method of claim 16, further comprising:

ultrasonically welding metal package terminals to the first and second DMB ceramic substrates.