Amplitude modulation for pass gate to improve charge pump efficiency

• US 9,083,231 B2
• Filed: 09/30/2013
• Issued: 07/14/2015
• Est. Priority Date: 09/30/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Pan, Feng, Huynh, Jonathan, Wang, Sung-En, Lei, Bo
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US14/041,522
• Publication Number:
  US 20150091637A1
• Time in Patent Office: 652 Days
• Field of Search: 327/536
• US Class Current: 1/1
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/076 the clock signals being boosted to a value being higher than the input voltage value

Abstract

Techniques are presented for improving the efficiency of charge pumps. A charge pump, or a stage of a charge pump, provides its output through a pass gate. For example, this could be a charge pump of a voltage doubler type, where the output is supplied through pass gate transistors whose gates are connected to receive the output of an auxiliary section, also of a voltage doubler type of design. The waveforms provided to the gates of the pass gate transistors are modified so that their low values are offset to a higher value to take into account the threshold voltage of the pass gate transistors. In a voltage doubler based example, this can be implemented by way of introducing diodes into each leg of the auxiliary section.

Claims

1. A method of operating a charge pump circuit, the charge pump including one or more stages each having one or more legs, including a first leg connected between an output node for the corresponding stage and an input node for the corresponding stage receiving an input voltage for the stage, and the first leg has a first capacitor with a first plate connected to an internal node thereof and a first output transistor connected between the internal node and the output node of the corresponding stage, the method comprising:

applying a first clock signal to a second plate of first capacitor, the first clock signals value alternating between a high value and a low value;

applying a second clock signal to the gate of the first output transistor, wherein the second clock signal is of the same phase as the first clock signal, and wherein the second clock signal has a low value that is higher than the input voltage for the stage, being offset above the input voltage by an amount not more than the than the threshold voltage of the first output transistor; and

generating the second clock signal from the first clock signal using an auxiliary charge pump section including one or more stages each having one or more legs, the second clock signal being generated by a first of the legs thereof,

wherein the first leg of the auxiliary charge pump section is connected to ground through a diode, whereby the voltage offset is implemented.

2. The method of claim 1, wherein the second clock signal has a high value not lower than value at the internal node when the first clock signal is high.

3. The method of claim 1, wherein the voltage offset is set to be the threshold voltage of the first output transistor.

4. The method of claim 1, wherein the stage to which the first leg belongs further includes a second leg connected in parallel with the first leg between the input and output nodes for the corresponding stage, the first and second legs being connected according to a voltage doubler arrangement.

5. The method of claim 1, wherein the change pump includes multiple stages connected in series, where the output node of the last stage in the series provides the output of the charge pump and where, for each stage except for the last of the series, the output node of each stage is connected to the input node of the subsequent stage.

6. The method of claim 1, wherein the stages of the series alternately receive one of two non-overlapping first clock signals.

7. A method of operating a charge pump circuit, the charge pump including one or more stages each having one or more legs, including a first leg connected between an output node for the corresponding stage and an input node for the corresponding stage receiving an input voltage for the stage, and the first leg has a first capacitor with a first plate connected to an internal node thereof and a first output transistor connected between the internal node and the output node of the corresponding stage, the method comprising:

applying a first clock signal to a second plate of first capacitor, the first clock signals value alternating between a high value and a low value;

applying a second clock signal to the first output transistor, wherein the second clock signal is of the same phase as the first clock signal, and wherein the second clock signal has a low value that is higher than the input voltage for the stage, being offset above the input voltage by an amount not more than the than the threshold voltage of the first output transistor; and

generating the second clock signal from the first clock signal using an auxiliary charge pump section including one or stages each having one or more legs, the second signal being generated by a first of the legs thereof,

wherein the first leg of the auxiliary charge pump section is connected to ground through a transistor whose gate is biased to a level to provide the offset voltage.

8. The method of claim 7, wherein the second clock signal has a high value not lower than value at the internal node when the first clock signal is high.

9. The method of claim 7, wherein the voltage offset is set to be the threshold voltage of the first output transistor.

10. The method of claim 7, wherein the stage to which the first leg belongs further includes a second leg connected in parallel with the first leg between the input and output nodes for the corresponding stage, the first and second legs being connected according to a voltage doubler arrangement.

11. The method of claim 7, wherein the change pump includes multiple stages connected in series, where the output node of the last stage in the series provides the output of the charge pump and where, for each stage except for the last of the series, the output node of each stage is connected to the input node of the subsequent stage.

12. The method of claim 7, wherein the stages of the series alternately receive one of two non-overlapping first clock signals.