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Soft error resilient circuit design method and logic cells

  • US 9,083,341 B2
  • Filed: 12/03/2012
  • Issued: 07/14/2015
  • Est. Priority Date: 01/17/2008
  • Status: Active Grant
First Claim
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1. A computer-implemented method of creating a logic integrated circuit cell from an original logic integrated circuit cell, the method comprising:

  • combining, by a processor, the original logic integrated circuit cell with a second integrated circuit cell, wherein the inputs of the second integrated circuit cell are the complement of each of the inputs of the original logic integrated circuit cell and the output of the second integrated circuit cell is the complement of the output of the original logic integrated circuit cell;

    connecting, by the processor, the combined logic integrated circuit cell, to one or more other combined logic integrated circuit cell, such that the output of the original logic integrated circuit cell from the combined logic integrated circuit cell is connected to the inputs of the one or more other combined logic integrated circuit cells, and the output of the second integrated circuit cell from the combined integrated circuit cell is connected to the inputs of the one or more other combined logic integrated circuit cells as the complement of the output from the original logic integrated circuit cell; and

    simplifying, by the processor, the combined logic integrated circuit cell, wherein simplifying the combined logic integrated circuit cell comprises;

    disconnecting, by the processor, each circuit node in the combined logic integrated circuit cell, which has a voltage value equal to the complement of one of the inputs to the original logic integrated circuit cell, from the circuit portion that provides the input to each of these circuit nodes; and

    connecting, by the processor, the disconnected circuit nodes to an external signal with this voltage value.

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