Soft error resilient circuit design method and logic cells
First Claim
1. A computer-implemented method of creating a logic integrated circuit cell from an original logic integrated circuit cell, the method comprising:
- combining, by a processor, the original logic integrated circuit cell with a second integrated circuit cell, wherein the inputs of the second integrated circuit cell are the complement of each of the inputs of the original logic integrated circuit cell and the output of the second integrated circuit cell is the complement of the output of the original logic integrated circuit cell;
connecting, by the processor, the combined logic integrated circuit cell, to one or more other combined logic integrated circuit cell, such that the output of the original logic integrated circuit cell from the combined logic integrated circuit cell is connected to the inputs of the one or more other combined logic integrated circuit cells, and the output of the second integrated circuit cell from the combined integrated circuit cell is connected to the inputs of the one or more other combined logic integrated circuit cells as the complement of the output from the original logic integrated circuit cell; and
simplifying, by the processor, the combined logic integrated circuit cell, wherein simplifying the combined logic integrated circuit cell comprises;
disconnecting, by the processor, each circuit node in the combined logic integrated circuit cell, which has a voltage value equal to the complement of one of the inputs to the original logic integrated circuit cell, from the circuit portion that provides the input to each of these circuit nodes; and
connecting, by the processor, the disconnected circuit nodes to an external signal with this voltage value.
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Accused Products
Abstract
A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell. The method further includes connecting the combined logic integrated circuit cells, where the outputs of the combined integrated circuit cells provide the inputs for other combined circuit cells such that, when the output of the original logic integrated circuit from a first combined logic integrated circuit cell is connected as input to a second combined logic integrated circuit cell, then the output of the second circuit in the first combined logic integrated circuit cell is always also connected to the second combined logic integrated circuit cell serving as the inverse of the input signals that come from the original logic integrated circuit cell.
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Citations
13 Claims
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1. A computer-implemented method of creating a logic integrated circuit cell from an original logic integrated circuit cell, the method comprising:
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combining, by a processor, the original logic integrated circuit cell with a second integrated circuit cell, wherein the inputs of the second integrated circuit cell are the complement of each of the inputs of the original logic integrated circuit cell and the output of the second integrated circuit cell is the complement of the output of the original logic integrated circuit cell; connecting, by the processor, the combined logic integrated circuit cell, to one or more other combined logic integrated circuit cell, such that the output of the original logic integrated circuit cell from the combined logic integrated circuit cell is connected to the inputs of the one or more other combined logic integrated circuit cells, and the output of the second integrated circuit cell from the combined integrated circuit cell is connected to the inputs of the one or more other combined logic integrated circuit cells as the complement of the output from the original logic integrated circuit cell; and simplifying, by the processor, the combined logic integrated circuit cell, wherein simplifying the combined logic integrated circuit cell comprises; disconnecting, by the processor, each circuit node in the combined logic integrated circuit cell, which has a voltage value equal to the complement of one of the inputs to the original logic integrated circuit cell, from the circuit portion that provides the input to each of these circuit nodes; and connecting, by the processor, the disconnected circuit nodes to an external signal with this voltage value. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor integrated circuit, implemented by a computer-implemented method of creating a logic integrated circuit cell from an original logic integrated circuit cell, the method comprising:
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combining, by a processor, the original logic integrated circuit cell with a second integrated circuit cell, wherein the inputs of the second integrated circuit cell are the complement of each of the inputs of the original logic integrated circuit cell and the output of the second integrated circuit cell is the complement of the output of the original logic integrated circuit cell; connecting, by the processor, the combined logic integrated circuit cell, to one or more other combined logic integrated circuit cell, such that the output of the original logic integrated circuit cell from the combined logic integrated circuit cell is connected to the inputs of the one or more other combined logic integrated circuit cells, and the output of the second integrated circuit cell from the combined integrated circuit cell is connected to the inputs of the one or more other combined logic integrated circuit cells as the complement of the output from the original logic integrated circuit cell, wherein the semiconductor integrated circuit, comprises; a physical arrangement where contact areas of one or more devices have been placed along a line in a substrate, and where n-type contact areas of the combined logic integrated circuit cell, which are connected to an output (q) of the original logic integrated circuit cell (n-q), and connected to an output (qi) of the second integrated circuit cell (n-qi), and p-type contact areas of the combined logic integrated circuit cell, which are connected to q (p-q) and to qi (p-qi), are ordered along the line in the substrate such that in-between an n-q node and a p-qi node there is always at least one n-qi node and/or at least one p-q node, and such that in-between an n-qi node and a p-q node there is always at least one n-q node and/or at least one p-qi node; wherein the logic integrated circuit cell implements an exclusive OR (XOR) logic function using complementary metal-oxide-semiconductor (CMOS) technology, the logic circuit cell comprising; eight n-type MOS field-effect-transistors (FET) (MOSFET) devices and eight p-type MOSFET devices; four input signals a, b, ai, bi, wherein ai is the inverse complement of a, and bi is the inverse complement of b; a power node (VDD), which is connected to a high voltage for the logic circuit cell and a ground node (GND), which is connected to a low voltage for the logic circuit cell; and two output nodes, q and qi, wherein qi is the inverse complement of q. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification